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AMD x86 manual Instruction Decoding Optimizations, Overview

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22007E/0 — November 1999

AMD Athlon™ Processor x86 Code Optimization

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Instruction Decoding

Optimizations

This chapter discusses ways to maximize the number of instructions decoded by the instruction decoders in the AMD Athlon™ processor. Guidelines are listed in order of importance.

Overview

The AMD Athlon processor instruction fetcher reads 16-byte aligned code windows from the instruction cache. The instruction bytes are then merged into a 24-byte instruction queue. On each cycle, the in-order front-end engine selects for decode up to three x86 instructions from the instruction-byte queue.

All instructions (x86, x87, 3DNow!™, and MMX™) are classified into two types of decodes — DirectPath and VectorPath (see “DirectPath Decoder” and “VectorPath Decoder” on page 133 for more information). DirectPath instructions are common instructions that are decoded directly in hardware. VectorPath instructions are more complex instructions that require the use of a sequence of multiple operations issued from an on-chip ROM.

Up to three DirectPath instructions can be selected for decode per cycle. Only one VectorPath instruction can be selected for decode per cycle. DirectPath instructions and VectorPath instructions cannot be simultaneously decoded.

Overview

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AMD x86 manual Instruction Decoding Optimizations, Overview

Contents

AMD AthlonTM Processor Trademarks Contents Instruction Decoding Optimizations Cache and Memory Optimizations Scheduling Optimizations Floating-Point Optimizations General x86 Optimization Guidelines 127 Appendix B Pipeline and Execution Unit Resources Overview Appendix E Programming the Mtrr and PAT List of Figures Xii List of Tables Xiv Revision History Xvi About this Document IntroductionSource Level Optimizations. Describes optimizations that AMD Athlon Processor Family AMD Athlon Processor Microarchitecture Summary AMD Athlon Processor Microarchitecture Summary AMD Athlon Processor x86 Code Optimization Top Optimizations Optimization Star Memory Size and Alignment IssuesGroup I Optimizations Essential Optimizations Use the 3DNow! Prefetch and Prefetchw InstructionsSelect DirectPath Over VectorPath Instructions Group II Optimizations-Secondary OptimizationsLoad-Execute Instruction Usage Use Load-Execute InstructionsUse 3DNow! Instructions Take Advantage of Write CombiningAvoid Branches Dependent on Random Data Avoid Placing Code and Data in the Same 64-Byte Cache Line 22007E/0 November Use 32-Bit Data Types for Integer Code Source Level OptimizationsExample 1 Avoid Consider the Sign of Integer OperandsExample Preferred Example Avoid Use Array Style Instead of Pointer Style CodeUse unsigned types for Use signed types forVertex Example 2 Preferred Avoid Unnecessary Store-to-Load Dependencies Completely Unroll Small LoopsAvoid Unnecessary Store-to-Load Dependencies Consider Expression Order in Compound Branch Conditions Optimize Switch Statements Switch Statement UsageUse Prototypes for All Functions Generic Loop Hoisting Use Const Type QualifierExample Generalization for Multiple Constant Control Code Declare Local Functions as Static Introduce Explicit Parallelism into Code Dynamic Memory Allocation ConsiderationExplicitly Extract Common Subexpressions Example Language Structure Component ConsiderationsAvoid PreferredOriginal ordering Avoid Sort Local Variables According to Base Type SizeNew ordering, with padding Preferred Improved ordering Preferred Accelerating Floating-Point Divides and Square RootsAccelerating Floating-Point Divides and Square Roots Avoid Unnecessary Integer Division AMD Athlon Processor x86 Code Optimization Overview Instruction Decoding OptimizationsLoad-Execute Instruction Usage Select DirectPath Over VectorPath InstructionsUse Load-Execute Integer Instructions TOP Use Short Instruction Lengths Align Branch Targets in Program Hot SpotsExample 2 Avoid Avoid Partial Register Reads and WritesReplace Certain Shld Instructions with Alternative Code Use 8-Bit Sign-Extended ImmediatesCode Padding Using Neutral Code Fillers Use 8-Bit Sign-Extended DisplacementsRecommendations for the AMD Athlon Processor Code Padding Using Neutral Code Fillers AMD Athlon Processor x86 Code Optimization NOP6EDI AMD Athlon Processor x86 Code Optimization Cache and Memory Optimizations Memory Size and Alignment IssuesAvoid Memory Size Mismatches Use the 3DNow! Prefetch and Prefetchw Instructions Align Data Where PossibleCode Example Multiple PrefetchesMOV ECX, -LARGENUM Prefetch Distance = 200 DS/C bytes Determining Prefetch DistanceAvoid Placing Code and Data in the Same 64-Byte Cache Line Take Advantage of Write CombiningStore-to-Load Forwarding Pitfalls -True Dependencies Store-to-Load Forwarding RestrictionsExample 4 Avoid Example 3 AvoidExample 6 Avoid Example 5 PreferredExample 7 Avoid Summary of Store-to-Load Forwarding Pitfalls to Avoid Stack Alignment ConsiderationsAlign Tbyte Variables on Quadword Aligned Addresses Sort Variables According to Base Type Size Avoid Branches Dependent on Random Data Branch OptimizationsBlended AMD-K6and AMD Athlon Processor Code AMD Athlon Processor Specific CodeExample 6 Increment Ring Buffer Offset Always Pair Call and ReturnExample 7 Integer Signum Function Muxing Constructs Replace Branches with Computation in 3DNow! CodeCode Sample Code Translated into 3DNow! Code3DNow! code MM5 Pfsub Psrad Avoid Far Control Transfer Instructions Avoid the Loop InstructionAvoid Recursive Functions Schedule Instructions According to their Latency Scheduling OptimizationsUnrolling Loops Complete Loop UnrollingPartial Loop Unrolling With Partial Loop Unrolling Without Loop UnrollingControl For Partially Deriving LoopUnrolled Loops Example 1 rolled loopOverview Use Function InliningAlways Inline Functions if Called from One Site Avoid Address Generation InterlocksMinimize Pointer Arithmetic in Loops Use Movzx and MovsxMOV ECX, Maxsize Example 3 Preferred Push Memory Data CarefullyPush Memory Data Carefully Replace Divides with Multiplies Integer OptimizationsMultiplication by Reciprocal Division Utility Unsigned Division by Multiplication of Constant Simpler Code for Signed Division by Multiplication of ConstantRestricted Dividend Signed Division By 2n Signed Division ByRemainder of Signed Integer 2 orInteger 2n or -2n Use Alternative Code When Multiplying by a ConstantADD REG1, REG1 REG1, REG2 SHL Use MMX Instructions for Integer-Only Work Latency of Repeated String Instructions Repeated String Instruction UsageGuidelines for Repeated String Instructions Ensure DF=0 UP Using MovqAlign Source Destination withEfficient 64-Bit Integer Arithmetic Use XOR Instruction to Clear Integer RegistersExample 5 Right shift Example 4 Left shiftExample 6 Multiplication EBX, ESP+12 Dividendlo Example 7 DivisionExample 8 Remainder SHR EDX Step Efficient Implementation of Population Count FunctionBit field. Thus the following computation is performed MOV EDX, EDX SHR Derivation of Multiplier Used for Integer Division by Utility sdiv.exe was compiled using the following code MOV ECX EDX Imul ADD SHR SAR Ensure All FPU Data is Aligned Floating-Point OptimizationsUse Multiplies Rather than Divides Use Ffreep Macro to Pop One Register from the FPU Stack Floating-Point Compare InstructionsUse the Fxch Instruction Rather than FST/FLD Pairs Avoid Using Extended-Precision DataExample 1 Fast Minimize Floating-Point-to-Integer ConversionsExample 2 Potentially faster Example 4 Fastest Example 3 Potentially fasterFloating-Point Subexpression Elimination 104 Take Advantage of the Fsincos Instruction 106 Use 3DNow! Instructions 3DNow! and MMX OptimizationsUse Femms Instruction Optimized 14-Bit Precision Divide Use 3DNow! Instructions for Fast DivisionOptimized Full 24-Bit Precision Divide Newton-Raphson Reciprocal Pipelined Pair of 24-Bit Precision DividesOptimized 24-Bit Precision Square Root Optimized 15-Bit Precision Square RootNewton-Raphson Reciprocal Square Root AMD Athlon 3DNow! and MMX Intra-Operand SwappingSpecific Code Blended CodeUse MMX Pxor to Negate 3DNow! Data Fast Conversion of Signed Words to Floating-PointBoth Numbers Use MMX Pcmp Instead of 3DNow! PfcmpPositive One Negative, One PositiveAMD-K6and AMD Athlon Processor Blended Code Use MMX Instructions for Block Copies and Block Fills116 Processor Specific Use MMX Pxor to Clear All Bits in an MMX Register Use MMX Pcmpeqd to Set All Bits in an MMX Register Optimized Matrix MultiplicationMOV EBX, RES Optimized Matrix Multiplication 121 Data Use 3DNow! Pavgusb for MPEG-2 Motion Compensation MM0=QWORD1 Stream of Packed Unsigned Bytes Complex Number Arithmetic Short Forms General x86 Optimization GuidelinesRegister Operands DependenciesStack Allocation Introduction AMD Athlon Processor MicroarchitectureSuperscalar Processor AMD Athlon Processor MicroarchitectureAMD Athlon Processor Microarchitecture 131 Branch Prediction PredecodeEarly Decoding Data Cache Instruction Control UnitInteger Execution Unit Integer SchedulerFloating-Point Scheduler 12 to Floating-Point Execution UnitLoad/Store Unit Load-Store Unit LSUWrite Combining L2 Cache ControllerAMD Athlon System Bus 140 AMD Athlon Processor Microarchitecture Fetch and Decode Pipeline Stages Pipeline and Execution Unit Resources OverviewC T L R O M Cycle 2-SCAN Cycle 1-FETCHCycle 3 DirectPath Cycle 3 VectorPathInteger Pipeline Stages Integer Pipeline StagesCycle 8-EXEC Cycle 7-SCHEDCycle 9-ADDGEN Cycle 10 -DCACCFloating-Point Pipeline Stages Floating-Point Pipeline StagesCycle 8-REGREN Cycle 7-STKRENCycle 9-SCHEDW Cycle 10 -SCHEDTerminology Execution Unit ResourcesOperands ResultsInteger Pipeline Operation Types Integer Pipeline OperationsInteger Decode Types Floating-Point Pipeline Operation Types Floating-Point Pipeline OperationsFloating-Point Decode Types Load/Store Unit Stages Load/Store Pipeline OperationsStage 1 Cycle Stage 2 Cycle Stage 3 Cycle Code Sample Analysis ADD EDI, EBX SHL Imul EAX, ECX INC ESI MOVINC EBX ADD ESI, EDX DEC EDX MOV EDI, ECX SUB Sample 2 Integer Register and Memory Load OperationsSAR Implementation Write Combining Appendix CWrite-Combining Definitions and Abbreviations What is Write Combining?Programming Details Write-Combining Operations INIT, Halt Write Combining Completion EventsSending Write-Buffer Data to the System AMD Athlon System Bus Commands Generation Rules160 Write-Combining Operations Performance Counter Usage Performance-Monitoring CountersPerfEvtSel30 Registers PerfEvtSel30 MSRs MSR Addresses C0010000h-C0010003hPerformance Counter Usage 163 Performance-Monitoring Counters 73h 65hSnoop hits 74hWaited to use the L2 Event Source Event DescriptionInstruction cache fetches Instruction cache missesPerfCtr30 MSRs MSR Addresses C0010004h-C0010007h Starting and Stopping the Performance-Monitoring Counters Event and Time-Stamp Monitoring SoftwareMonitoring Counter Overflow 170 Monitoring Counter Overflow Memory Type Range Register Mtrr Mechanism Programming the Mtrr172 Memory Type Range Register Mtrr Mechanism FFFFFFFFh Fixed Ranges100000h Kbytes each Fixed Ranges C0000h 80000h Memory Type Encodings Memory TypesMtrr Capability Register FormatMemory Type Range Register Mtrr Mechanism 175 Standard Mtrr Types and Properties Attribute Table MSR 277h Attribute Table PATPATi 3-Bit Encodings PAT Entry Reset ValueMTRRs and PAT PATiPAT Memory Type Mtrr Memory Type Effective Memory Type Based on PAT and MTRRsInput Memory Type Final Output Memory TypesAttribute Table PAT 181 9FFFF 9BFFF 97FFF 93FFF 8FFFF 8BFFF 87FFF 83FFF 7FFFF 6FFFF 5FFFF 4FFFF 3FFFF 2FFFF 1FFFF 0FFFFBffff Bbfff B7FFF B3FFF Affff Abfff A7FFF A3FFF C7FFF C6FFF C5FFF C4FFF C3FFF C2FFF C1FFF C0FFFAttribute Table PAT 183 MTRRphysMaskn Register Format MTRR-Related Model-Specific Register MSR Map 186 Instruction Dispatch Execution Resources Appendix FAAA Integer InstructionsAAD AAMADC mreg8, reg8 ModR/M Decode ByteADC mem8, reg8 ADC mreg16/32, reg16/32Bswap EAX BoundBswap ECX Bswap EDXCLC CBW/CWDECLD CLICMOVE/CMOVZ reg16/32, mem16/32 0Fh CMOVE/CMOVZ reg16/32, reg16/32 0FhCMOVG/CMOVNLE reg16/32, reg16/32 0Fh CMOVG/CMOVNLE reg16/32, mem16/32 0FhCWD/CDQ CpuidDAA DASAL, DX EnterAX, DX EAX, DXInvlpg InvdLeave LahfLOOPNE/LOOPNZ disp8 E0h LOOPE/LOOPZ disp8 E1hLSL reg16/32, mreg16/32 0Fh 03h LSL reg16/32, mem16/32 0Fh 03hNOP Xchg EAX, EAX OUT DX, AX OUT DX, ALOUT DX, EAX POP ESPOP ESP POP EBXPOP EBP POP ESIRdpmc RdmsrRdtsc Sahf SBB mem16/32, reg16/32 SBB mreg16/32, reg16/32SBB reg8, mreg8 SBB reg8, mem8Sets mem8 Sets mreg8Setns mreg8 Setns mem8STD STCSTI Sysenter SyscallSysexit SysretXchg EAX, ECX Xchg EAX, EAXXchg EAX, EDX Xchg EAX, EBXEmms MMX InstructionsDFh Pandn mmreg1, mmreg2Pandn mmreg, mem64 Pcmpeqb mmreg1, mmreg2FADD/FMUL FPU MMX ExtensionsFloating-Point Instructions Fcos FcomppFdecstp Finit FincstpFLD1 FLDL2T FLDL2EFLDLG2 FLDLN2Ftst Fstsw AXFucom FucompFemms DNow! InstructionsDNow! Extensions DirectPath Instructions DirectPath versus VectorPath InstructionsBT mreg16/32, reg16/32 BT mreg16/32, imm8 BT mem16/32, imm8 DirectPath Integer InstructionsCBW/CWDE CLC CMC INC mreg8 INC mem8 INC mreg16/32 INC mem16/32 JO short disp8 DEC mreg8 DEC mem8 DEC mreg16/32 DEC mem16/32222 DirectPath Instructions DirectPath Instructions 223 224 DirectPath Instructions Wait Xchg EAX, EAX 226 DirectPath Instructions DirectPath MMX Instructions DirectPath MMX Extensions Fcompp Fdecstp DirectPath Floating-Point InstructionsFist mem16int FLD1 FLDL2E FLDL2T FLDLG2 FLDLN2 Fldpi FldzFtst Fucom Fucomp Fucompp Fwait Fxch VectorPath Integer Instructions VectorPath InstructionsAAA AAD AAM AAS CLD CLI CltsAL, DX AX, DX EAX, DX Invd Invlpg Instruction Mnemonic DIV EAX, mem16/32Push mreg16/32 Push mem16/32 POP mreg 16/32 POP mem 16/32PUSHA/PUSHAD PUSHF/PUSHFD Rdmsr Rdpmc RdtscVectorPath MMX Extensions VectorPath MMX InstructionsSyscall Sysenter Sysexit Sysret Wbinvd WrmsrFptan Fpatan Frndint VectorPath Floating-Point InstructionsFscale Fsin Fsincos Fxam Fxtract FYL2X FYL2XP1236 Index 238 Index Index 239 240 Index