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AMD x86 manual Programming the Mtrr, Memory Type Range Register Mtrr Mechanism

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22007E/0 — November 1999

AMD Athlon™ Processor x86 Code Optimization

Appendix E

Programming the MTRR and

PAT

Introduction

The AMD Athlon™ processor includes a set of memory type and range registers (MTRRs) to control cacheability and access to specified memory regions. The processor also includes the Page Address Table for defining attributes of pages. This chapter documents the use and capabilities of this feature.

The purpose of the MTRRs is to provide system software with the ability to manage the memory mapping of the hardware. Both the BIOS software and operating systems utilize this capability. The AMD Athlon processor’s implementation is compatible to the Pentium® II. Prior to the MTRR mechanism, chipsets usually provided this capability.

Memory Type Range Register (MTRR) Mechanism

The memory type and range registers allow the processor to determine cacheability of various memory locations prior to bus access and to optimize access to the memory system. The AMD Athlon processor implements the MTRR programming model in a manner compatible with Pentium II.

Introduction

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AMD x86 manual Programming the Mtrr, Memory Type Range Register Mtrr Mechanism

Contents

AMD AthlonTM Processor Trademarks Contents Instruction Decoding Optimizations Cache and Memory Optimizations Scheduling Optimizations Floating-Point Optimizations General x86 Optimization Guidelines 127 Appendix B Pipeline and Execution Unit Resources Overview Appendix E Programming the Mtrr and PAT List of Figures Xii List of Tables Xiv Revision History Xvi About this Document IntroductionSource Level Optimizations. Describes optimizations that AMD Athlon Processor Family AMD Athlon Processor Microarchitecture Summary AMD Athlon Processor Microarchitecture Summary AMD Athlon Processor x86 Code Optimization Top Optimizations Use the 3DNow! Prefetch and Prefetchw Instructions Memory Size and Alignment IssuesOptimization Star Group I Optimizations Essential OptimizationsUse Load-Execute Instructions Group II Optimizations-Secondary OptimizationsSelect DirectPath Over VectorPath Instructions Load-Execute Instruction UsageUse 3DNow! Instructions Take Advantage of Write CombiningAvoid Branches Dependent on Random Data Avoid Placing Code and Data in the Same 64-Byte Cache Line 22007E/0 November Use 32-Bit Data Types for Integer Code Source Level OptimizationsExample 1 Avoid Consider the Sign of Integer OperandsExample Preferred Use signed types for Use Array Style Instead of Pointer Style CodeExample Avoid Use unsigned types forVertex Example 2 Preferred Avoid Unnecessary Store-to-Load Dependencies Completely Unroll Small LoopsAvoid Unnecessary Store-to-Load Dependencies Consider Expression Order in Compound Branch Conditions Optimize Switch Statements Switch Statement UsageUse Prototypes for All Functions Generic Loop Hoisting Use Const Type QualifierExample Generalization for Multiple Constant Control Code Declare Local Functions as Static Introduce Explicit Parallelism into Code Dynamic Memory Allocation ConsiderationExplicitly Extract Common Subexpressions Preferred Language Structure Component ConsiderationsExample AvoidOriginal ordering Avoid Sort Local Variables According to Base Type SizeNew ordering, with padding Preferred Improved ordering Preferred Accelerating Floating-Point Divides and Square RootsAccelerating Floating-Point Divides and Square Roots Avoid Unnecessary Integer Division AMD Athlon Processor x86 Code Optimization Overview Instruction Decoding OptimizationsLoad-Execute Instruction Usage Select DirectPath Over VectorPath InstructionsUse Load-Execute Integer Instructions TOP Use Short Instruction Lengths Align Branch Targets in Program Hot SpotsExample 2 Avoid Avoid Partial Register Reads and WritesReplace Certain Shld Instructions with Alternative Code Use 8-Bit Sign-Extended ImmediatesCode Padding Using Neutral Code Fillers Use 8-Bit Sign-Extended DisplacementsRecommendations for the AMD Athlon Processor Code Padding Using Neutral Code Fillers AMD Athlon Processor x86 Code Optimization NOP6EDI AMD Athlon Processor x86 Code Optimization Cache and Memory Optimizations Memory Size and Alignment IssuesAvoid Memory Size Mismatches Use the 3DNow! Prefetch and Prefetchw Instructions Align Data Where PossibleCode Example Multiple PrefetchesMOV ECX, -LARGENUM Prefetch Distance = 200 DS/C bytes Determining Prefetch DistanceAvoid Placing Code and Data in the Same 64-Byte Cache Line Take Advantage of Write CombiningStore-to-Load Forwarding Pitfalls -True Dependencies Store-to-Load Forwarding RestrictionsExample 4 Avoid Example 3 AvoidExample 6 Avoid Example 5 PreferredExample 7 Avoid Summary of Store-to-Load Forwarding Pitfalls to Avoid Stack Alignment ConsiderationsAlign Tbyte Variables on Quadword Aligned Addresses Sort Variables According to Base Type Size Avoid Branches Dependent on Random Data Branch OptimizationsBlended AMD-K6and AMD Athlon Processor Code AMD Athlon Processor Specific CodeExample 6 Increment Ring Buffer Offset Always Pair Call and ReturnExample 7 Integer Signum Function Muxing Constructs Replace Branches with Computation in 3DNow! CodeCode Sample Code Translated into 3DNow! Code3DNow! code MM5 Pfsub Psrad Avoid Far Control Transfer Instructions Avoid the Loop InstructionAvoid Recursive Functions Complete Loop Unrolling Scheduling OptimizationsSchedule Instructions According to their Latency Unrolling LoopsPartial Loop Unrolling With Partial Loop Unrolling Without Loop UnrollingExample 1 rolled loop Deriving LoopControl For Partially Unrolled LoopsOverview Use Function InliningAlways Inline Functions if Called from One Site Avoid Address Generation InterlocksMinimize Pointer Arithmetic in Loops Use Movzx and MovsxMOV ECX, Maxsize Example 3 Preferred Push Memory Data CarefullyPush Memory Data Carefully Replace Divides with Multiplies Integer OptimizationsMultiplication by Reciprocal Division Utility Unsigned Division by Multiplication of Constant Simpler Code for Signed Division by Multiplication of ConstantRestricted Dividend Integer 2 or Signed Division BySigned Division By 2n Remainder of SignedInteger 2n or -2n Use Alternative Code When Multiplying by a ConstantADD REG1, REG1 REG1, REG2 SHL Use MMX Instructions for Integer-Only Work Latency of Repeated String Instructions Repeated String Instruction UsageGuidelines for Repeated String Instructions Destination with Using MovqEnsure DF=0 UP Align SourceEfficient 64-Bit Integer Arithmetic Use XOR Instruction to Clear Integer RegistersExample 5 Right shift Example 4 Left shiftExample 6 Multiplication EBX, ESP+12 Dividendlo Example 7 DivisionExample 8 Remainder SHR EDX Step Efficient Implementation of Population Count FunctionBit field. Thus the following computation is performed MOV EDX, EDX SHR Derivation of Multiplier Used for Integer Division by Utility sdiv.exe was compiled using the following code MOV ECX EDX Imul ADD SHR SAR Ensure All FPU Data is Aligned Floating-Point OptimizationsUse Multiplies Rather than Divides Use Ffreep Macro to Pop One Register from the FPU Stack Floating-Point Compare InstructionsUse the Fxch Instruction Rather than FST/FLD Pairs Avoid Using Extended-Precision DataExample 1 Fast Minimize Floating-Point-to-Integer ConversionsExample 2 Potentially faster Example 4 Fastest Example 3 Potentially fasterFloating-Point Subexpression Elimination 104 Take Advantage of the Fsincos Instruction 106 Use 3DNow! Instructions 3DNow! and MMX OptimizationsUse Femms Instruction Optimized 14-Bit Precision Divide Use 3DNow! Instructions for Fast DivisionOptimized Full 24-Bit Precision Divide Newton-Raphson Reciprocal Pipelined Pair of 24-Bit Precision DividesOptimized 24-Bit Precision Square Root Optimized 15-Bit Precision Square RootNewton-Raphson Reciprocal Square Root Blended Code 3DNow! and MMX Intra-Operand SwappingAMD Athlon Specific CodeUse MMX Pxor to Negate 3DNow! Data Fast Conversion of Signed Words to Floating-PointPositive Use MMX Pcmp Instead of 3DNow! PfcmpBoth Numbers Positive One Negative, OneAMD-K6and AMD Athlon Processor Blended Code Use MMX Instructions for Block Copies and Block Fills116 Processor Specific Use MMX Pxor to Clear All Bits in an MMX Register Use MMX Pcmpeqd to Set All Bits in an MMX Register Optimized Matrix MultiplicationMOV EBX, RES Optimized Matrix Multiplication 121 Data Use 3DNow! Pavgusb for MPEG-2 Motion Compensation MM0=QWORD1 Stream of Packed Unsigned Bytes Complex Number Arithmetic Short Forms General x86 Optimization GuidelinesRegister Operands DependenciesStack Allocation Introduction AMD Athlon Processor MicroarchitectureSuperscalar Processor AMD Athlon Processor MicroarchitectureAMD Athlon Processor Microarchitecture 131 Branch Prediction PredecodeEarly Decoding Data Cache Instruction Control UnitInteger Execution Unit Integer SchedulerFloating-Point Scheduler 12 to Floating-Point Execution UnitLoad/Store Unit Load-Store Unit LSUWrite Combining L2 Cache ControllerAMD Athlon System Bus 140 AMD Athlon Processor Microarchitecture Fetch and Decode Pipeline Stages Pipeline and Execution Unit Resources OverviewC T L R O M Cycle 3 VectorPath Cycle 1-FETCHCycle 2-SCAN Cycle 3 DirectPathInteger Pipeline Stages Integer Pipeline StagesCycle 10 -DCACC Cycle 7-SCHEDCycle 8-EXEC Cycle 9-ADDGENFloating-Point Pipeline Stages Floating-Point Pipeline StagesCycle 10 -SCHED Cycle 7-STKRENCycle 8-REGREN Cycle 9-SCHEDWResults Execution Unit ResourcesTerminology OperandsInteger Pipeline Operation Types Integer Pipeline OperationsInteger Decode Types Floating-Point Pipeline Operation Types Floating-Point Pipeline OperationsFloating-Point Decode Types Load/Store Unit Stages Load/Store Pipeline OperationsStage 1 Cycle Stage 2 Cycle Stage 3 Cycle Code Sample Analysis ADD EDI, EBX SHL Imul EAX, ECX INC ESI MOVINC EBX ADD ESI, EDX DEC EDX MOV EDI, ECX SUB Sample 2 Integer Register and Memory Load OperationsSAR Implementation Write Combining Appendix CWrite-Combining Definitions and Abbreviations What is Write Combining?Programming Details Write-Combining Operations INIT, Halt Write Combining Completion EventsSending Write-Buffer Data to the System AMD Athlon System Bus Commands Generation Rules160 Write-Combining Operations Performance Counter Usage Performance-Monitoring CountersPerfEvtSel30 Registers PerfEvtSel30 MSRs MSR Addresses C0010000h-C0010003hPerformance Counter Usage 163 Performance-Monitoring Counters 74h 65h73h Snoop hitsInstruction cache misses Event Source Event DescriptionWaited to use the L2 Instruction cache fetchesPerfCtr30 MSRs MSR Addresses C0010004h-C0010007h Starting and Stopping the Performance-Monitoring Counters Event and Time-Stamp Monitoring SoftwareMonitoring Counter Overflow 170 Monitoring Counter Overflow Memory Type Range Register Mtrr Mechanism Programming the Mtrr172 Memory Type Range Register Mtrr Mechanism FFFFFFFFh Fixed Ranges100000h Kbytes each Fixed Ranges C0000h 80000h Register Format Memory TypesMemory Type Encodings Mtrr CapabilityMemory Type Range Register Mtrr Mechanism 175 Standard Mtrr Types and Properties Attribute Table MSR 277h Attribute Table PATPATi PAT Entry Reset ValuePATi 3-Bit Encodings MTRRs and PATPAT Memory Type Mtrr Memory Type Effective Memory Type Based on PAT and MTRRsInput Memory Type Final Output Memory TypesAttribute Table PAT 181 C7FFF C6FFF C5FFF C4FFF C3FFF C2FFF C1FFF C0FFF 7FFFF 6FFFF 5FFFF 4FFFF 3FFFF 2FFFF 1FFFF 0FFFF9FFFF 9BFFF 97FFF 93FFF 8FFFF 8BFFF 87FFF 83FFF Bffff Bbfff B7FFF B3FFF Affff Abfff A7FFF A3FFFAttribute Table PAT 183 MTRRphysMaskn Register Format MTRR-Related Model-Specific Register MSR Map 186 Instruction Dispatch Execution Resources Appendix FAAM Integer InstructionsAAA AADADC mreg16/32, reg16/32 ModR/M Decode ByteADC mreg8, reg8 ADC mem8, reg8Bswap EDX BoundBswap EAX Bswap ECXCLI CBW/CWDECLC CLDCMOVG/CMOVNLE reg16/32, mem16/32 0Fh CMOVE/CMOVZ reg16/32, reg16/32 0FhCMOVE/CMOVZ reg16/32, mem16/32 0Fh CMOVG/CMOVNLE reg16/32, reg16/32 0FhDAS CpuidCWD/CDQ DAAEAX, DX EnterAL, DX AX, DXInvlpg InvdLeave LahfLSL reg16/32, mem16/32 0Fh 03h LOOPE/LOOPZ disp8 E1hLOOPNE/LOOPNZ disp8 E0h LSL reg16/32, mreg16/32 0Fh 03hNOP Xchg EAX, EAX POP ES OUT DX, ALOUT DX, AX OUT DX, EAXPOP ESI POP EBXPOP ESP POP EBPRdpmc RdmsrRdtsc Sahf SBB reg8, mem8 SBB mreg16/32, reg16/32SBB mem16/32, reg16/32 SBB reg8, mreg8Setns mem8 Sets mreg8Sets mem8 Setns mreg8STD STCSTI Sysret SyscallSysenter SysexitXchg EAX, EBX Xchg EAX, EAXXchg EAX, ECX Xchg EAX, EDXEmms MMX InstructionsPcmpeqb mmreg1, mmreg2 Pandn mmreg1, mmreg2DFh Pandn mmreg, mem64FADD/FMUL FPU MMX ExtensionsFloating-Point Instructions Fcos FcomppFdecstp Finit FincstpFLD1 FLDLN2 FLDL2EFLDL2T FLDLG2Fucomp Fstsw AXFtst FucomFemms DNow! InstructionsDNow! Extensions DirectPath Instructions DirectPath versus VectorPath InstructionsBT mreg16/32, reg16/32 BT mreg16/32, imm8 BT mem16/32, imm8 DirectPath Integer InstructionsCBW/CWDE CLC CMC INC mreg8 INC mem8 INC mreg16/32 INC mem16/32 JO short disp8 DEC mreg8 DEC mem8 DEC mreg16/32 DEC mem16/32222 DirectPath Instructions DirectPath Instructions 223 224 DirectPath Instructions Wait Xchg EAX, EAX 226 DirectPath Instructions DirectPath MMX Instructions DirectPath MMX Extensions FLD1 FLDL2E FLDL2T FLDLG2 FLDLN2 Fldpi Fldz DirectPath Floating-Point InstructionsFcompp Fdecstp Fist mem16intFtst Fucom Fucomp Fucompp Fwait Fxch CLD CLI Clts VectorPath InstructionsVectorPath Integer Instructions AAA AAD AAM AASAL, DX AX, DX EAX, DX Invd Invlpg Instruction Mnemonic DIV EAX, mem16/32Rdmsr Rdpmc Rdtsc POP mreg 16/32 POP mem 16/32Push mreg16/32 Push mem16/32 PUSHA/PUSHAD PUSHF/PUSHFDWbinvd Wrmsr VectorPath MMX InstructionsVectorPath MMX Extensions Syscall Sysenter Sysexit SysretFxam Fxtract FYL2X FYL2XP1 VectorPath Floating-Point InstructionsFptan Fpatan Frndint Fscale Fsin Fsincos236 Index 238 Index Index 239 240 Index