22007E/0 — November 1999

AMD Athlon™ Processor x86 Code Optimization

Table 11. Performance-Monitoring Counters (Continued)

Event

Source

Notes / Unit Mask (bits 15–8)

Event Description

Number

Unit

 

 

 

 

 

 

D5h

FR

 

ICU full

 

 

 

 

D6h

FR

 

Reservation stations full

 

 

 

 

D7h

FR

 

FPU full

 

 

 

 

D8h

FR

 

LS full

 

 

 

 

D9h

FR

 

All quiet stall

 

 

 

 

DAh

FR

 

Far transfer or resync branch pending

 

 

 

 

DCh

FR

 

Breakpoint matches for DR0

 

 

 

 

DDh

FR

 

Breakpoint matches for DR1

 

 

 

 

DEh

FR

 

Breakpoint matches for DR2

 

 

 

 

DFh

FR

 

Breakpoint matches for DR3

 

 

 

 

PerfCtr[3:0] MSRs (MSR Addresses C001_0004h–C001_0007h)

The performance-counter MSRs contain the event or duration counts for the selected events being counted. The RDPMC instruction can be used by programs or procedures running at any privilege level and in virtual-8086 mode to read these counters. The PCE flag in control register CR4 (bit 8) allows the use of this instruction to be restricted to only programs and procedures running at privilege level 0.

The RDPMC instruction is not serializing or ordered with other instructions. Therefore, it does not necessarily wait until all previous instructions have been executed before reading the counter. Similarly, subsequent instructions can begin execution before the RDPMC instruction operation is performed.

Only the operating system, executing at privilege level 0, can directly manipulate the performance counters, using the RDMSR and WRMSR instructions. A secure operating system would clear the PCE flag during system initialization, which disables direct user access to the performance-monitoring counters but provides a user-accessible programming interface that emulates the RDPMC instruction.

The WRMSR instruction cannot arbitrarily write to the performance-monitoring counter MSRs (PerfCtr[3:0]). Instead, the value should be treated as 64-bit sign extended, which

Performance Counter Usage

167

Page 183
Image 183
AMD x86 manual PerfCtr30 MSRs MSR Addresses C0010004h-C0010007h