AMD Athlon™ Processor x86 Code Optimization

22007E/0 — November 1999

allows writing both positive and negative values to the performance counters. The performance counters may be initialized using a 64-bit signed integer in the range -247and +247. Negative values are useful for generating an interrupt after a specific number of events.

Starting and Stopping the Performance-Monitoring Counters

The performance-monitoring counters are started by writing valid setup information in one or more of the PerfEvtSel[3:0] MSRs and setting the enable counters flag in the PerfEvtSel0 MSR. If the setup is valid, the counters begin counting following the execution of a WRMSR instruction, which sets the enable counter flag. The counters can be stopped by clearing the enable counters flag or by clearing all the bits in the PerfEvtSel[3:0] MSRs.

Event and Time-Stamp Monitoring Software

For applications to use the performance-monitoring counters and time-stamp counter, the operating system needs to provide an event-monitoring device driver. This driver should include procedures for handling the following operations:

Feature checking

Initialize and start counters

Stop counters

Read the event counters

Reading of the time stamp counter

The event monitor feature determination procedure must determine whether the current processor supports the performance-monitoring counters and time-stamp counter. This procedure compares the family and model of the processor returned by the CPUID instruction with those of processors known to support performance monitoring. In addition, the procedure checks the MSR and TSC flags returned to register EDX by the CPUID instruction to determine if the MSRs and the RDTSC instruction are supported.

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Event and Time-Stamp Monitoring Software

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AMD x86 manual Event and Time-Stamp Monitoring Software, Starting and Stopping the Performance-Monitoring Counters