AMD x86 manual Load/Store Pipeline Operations, Load/Store Unit Stages

22007E/0 — November 1999 AMD Athlon™ Processor x86 Code Optimization

Load/Store Pipeline Operations

The AMD Athlon processor decodes any instruction that references memory into primitive load/store operations. For example, consider the following code sample:

MOV	AX, [EBX]	;1 load MacroOP
PUSH	EAX	;1 store MacroOP
POP	EAX	;1 load MacroOP
ADD	[EAX], EBX	;1 load/store and 1 IEU MacroOPs
FSTP	[EAX]	;1 store MacroOP
MOVQ	[EAX], MM0	;1 store MacroOP

As shown in Table 6, the load/store unit (LSU) consists of a three-stage data cache lookup.

Table 6. Load/Store Unit Stages

Stage 1 (Cycle 8)	Stage 2 (Cycle 9)	Stage 3 (Cycle 10)
Address Calculation / LS1	Transport Address to Data	Data Cache Access / LS2
Scan	Cache	Data Forward

Loads and stores are first dispatched in order into a 12-entry deep reservation queue called LS1. LS1 holds loads and stores that are waiting to enter the cache subsystem. Loads and stores are allocated into LS1 entries at dispatch time in program order, and are required by LS1 to probe the data cache in program order. The AGUs can calculate addresses out of program order, therefore, LS1 acts as an address reorder buffer.

When a load or store is scanned out of the LS1 queue (Stage 1), it is deallocated from the LS1 queue and inserted into the data cache probe pipeline (Stage 2 and Stage 3). Up to two memory operations can be scheduled (scanned out of LS1) to access the data cache per cycle. The LSU can handle the following:

■Two 64-bit loads per cycle or

■One 64-bit load and one 64-bit store per cycle or

■Two 32-bit stores per cycle

Execution Unit Resources 151