AMD x86 manual Appendix B Pipeline and Execution Unit Resources Overview

22007E/0 — November 1999

AMD Athlon™ Processor x86 Code Optimization

Integer Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Floating-Point Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . 137

Load-Store Unit (LSU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

L2 Cache Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Write Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

AMD Athlon System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Appendix B	Pipeline and Execution Unit Resources Overview	141
	Fetch and Decode Pipeline Stages	141
	Integer Pipeline Stages	144
	Floating-Point Pipeline Stages	146
	Execution Unit Resources	148
	Terminology	148
	Integer Pipeline Operations	149
	Floating-Point Pipeline Operations	150
	Load/Store Pipeline Operations	151
	Code Sample Analysis	152
Appendix C	Implementation of Write Combining	155
	Introduction	155
	Write-Combining Definitions and Abbreviations	156
	What is Write Combining?	156
	Programming Details	156
	Write-Combining Operations	157
	Sending Write-Buffer Data to the System	159
Appendix D	Performance-Monitoring Counters	161
	Overview	161
	Performance Counter Usage	161
	PerfEvtSel[3:0] MSRs
	(MSR Addresses C001_0000h–C001_0003h)	162

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