AMD x86 manual Performance Counter Usage 163

22007E/0 — November 1999 AMD Athlon™ Processor x86 Code Optimization

Unit Mask Field (Bits These bits are used to further qualify the event selected in the

8—15)event select field. For example, for some cache events, the mask is used as a MESI-protocol qualifier of cache states. See Table 11 on page 164 for a list of unit masks and their 8-bit codes.

USR (User Mode) Flag Events are counted only when the processor is operating at

(Bit 16)privilege levels 1, 2 or 3. This flag can be used in conjunction with the OS flag.

OS (Operating System Events are counted only when the processor is operating at

Mode) Flag (Bit 17) privilege level 0. This flag can be used in conjunction with the USR flag.

E (Edge Detect) Flag When this flag is set, edge detection of events is enabled. The

(Bit 18)processor counts the number of negated-to-asserted transitions of any condition that can be expressed by the other fields. The mechanism is limited in that it does not permit back-to-back assertions to be distinguished. This mechanism allows software to measure not only the fraction of time spent in a particular state, but also the average length of time spent in such a state (for example, the time spent waiting for an interrupt to be serviced).

PC (Pin Control) Flag When this flag is set, the processor toggles the PMi pins when

(Bit 19)the counter overflows. When this flag is clear, the processor toggles the PMi pins and increments the counter when performance monitoring events occur. The toggling of a pin is defined as assertion of the pin for one bus clock followed by negation.

INT (APIC Interrupt When this flag is set, the processor generates an interrupt

Enable) Flag (Bit 20) through its local APIC on counter overflow.

EN (Enable Counter) This flag enables/disables the PerfEvtSeln MSR. When set,

Flag (Bit 22)performance counting is enabled for this counter. When clear, this counter is disabled.

INV (Invert) Flag (Bit By inverting the Counter Mask Field, this flag inverts the result

23)of the counter comparison, allowing both greater than and less than comparisons.

Counter Mask Field For events which can have multiple occurrences within one

(Bits 31–24)clock, this field is used to set a threshold. If the field is non-zero, the counter increments each time the number of events is

Performance Counter Usage 163