AMD x86 manual List of Tables

22007E/0 — November 1999	AMD Athlon™ Processor x86 Code Optimization
List of Tables
Table 1.	Latency of Repeated String Instructions	. 84
Table 2.	Integer Pipeline Operation Types	149
Table 3.	Integer Decode Types	149
Table 4.	Floating-Point Pipeline Operation Types	150
Table 5.	Floating-Point Decode Types	150
Table 6.	Load/Store Unit Stages	151
Table 7.	Sample 1 – Integer Register Operations	153
Table 8.	Sample 2 – Integer Register and Memory Load
	Operations	154
Table 9.	Write Combining Completion Events	158
Table 10.	AMD Athlon™ System Bus Commands
	Generation Rules	159
Table 11.	Performance-Monitoring Counters	164
Table 12.	Memory Type Encodings	174
Table 13.	Standard MTRR Types and Properties	176
Table 14.	PATi 3-Bit Encodings	178
Table 15.	Effective Memory Type Based on PAT and
	MTRRs	179
Table 16.	Final Output Memory Types	180
Table 17.	MTRR Fixed Range Register Format	182
Table 18.	MTRR-RelatedModel-Specific Register
	(MSR) Map	185
Table 19.	Integer Instructions	188
Table 20.	MMX™ Instructions	208
Table 21.	MMX Extensions	211
Table 22.	Floating-Point Instructions	212
Table 23.	3DNow!™ Instructions	217
Table 24.	3DNow! Extensions	218
Table 25.	DirectPath Integer Instructions	220
Table 26.	DirectPath MMX Instructions	227
Table 27.	DirectPath MMX Extensions	228
Table 28.	DirectPath Floating-Point Instructions	229

List of Tables xiii