AMD Athlon™ Processor x86 Code Optimization

22007E/0 — November 1999

Floating-Point Pipeline Operations

Table 4 shows the category or type of operations handled by the floating-point execution units. Table 5 shows examples of the decode types.

Table 4. Floating-Point Pipeline Operation Types

Category

Execution Unit

 

 

FPU/3DNow!/MMX Load/store or

FSTORE

Miscellaneous Operations

 

 

 

FPU/3DNow!/MMX Multiply Operation

FMUL

 

 

FPU/3DNow!/MMX Arithmetic Operation

FADD

 

 

Table 5. Floating-Point Decode Types

x86 Instruction

Decode Type

OPs

 

 

 

FADD ST, ST(i)

DirectPath

FADD

 

 

 

FSIN

VectorPath

various

 

 

 

PFACC

DirectPath

FADD

 

 

 

PFRSQRT

DirectPath

FMUL

 

 

 

As shown in Table 4, the FADD register-to-register instruction generates a single MacroOP targeted for the floating-point scheduler. FSIN is considered a VectorPath instruction because it is a complex instruction with long execution times, as compared to the more common floating-point instructions. The MMX PFACC instruction is DirectPath decodeable and generates a single MacroOP targeted for the arithmetic operation execution pipeline in the floating-point logic. Just like PFACC, a single MacroOP is early decoded for the 3DNow! PFRSQRT instruction, but it is targeted for the multiply operation execution pipeline.

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Execution Unit Resources

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AMD x86 manual Floating-Point Pipeline Operations, Floating-Point Pipeline Operation Types, Floating-Point Decode Types