AMD x86 manual Code Sample Analysis

AMD Athlon™ Processor x86 Code Optimization 22007E/0 — November 1999

Code Sample Analysis

The samples in Table 7 on page 153 and Table 8 on page 154 show the execution behavior of several series of instructions as a function of decode constraints, dependencies, and execution resource constraints.

The sample tables show the x86 instructions, the decode pipe in the integer execution pipeline, the decode type, the clock counts, and a description of the events occurring within the processor. The decode pipe gives the specific IEU used (see Figure 7 on page 144). The decode type specifies either VectorPath (VP) or DirectPath (DP).

The following nomenclature is used to describe the current location of a particular operation:

■D—Dispatch stage (Allocate in ICU, reservation stations, load-store (LS1) queue)

■I—Issue stage (Schedule operation for AGU or FU execution)

■E—Integer Execution Unit (IEU number corresponds to decode pipe)

■&—Address Generation Unit (AGU number corresponds to decode pipe)

■M—Multiplier Execution

■S—Load/Store pipe stage 1 (Schedule operation for load/store pipe)

■A—Load/Store pipe stage 2 (1st stage of data cache/LS2 buffer access)

■$—Load/Store pipe stage 3 (2nd stage of data cache/LS2 buffer access)

Note: Instructions execute more efficiently (that is, without delays) when scheduled apart by suitable distances based on dependencies. In general, the samples in this section show poorly scheduled code in order to illustrate the resultant effects.

152 Execution Unit Resources