AMD x86 manual Write Combining Completion Events, INIT, Halt

AMD Athlon™ Processor x86 Code Optimization 22007E/0 — November 1999

Table 9. Write Combining Completion Events

Event	Comment
	The first non-WB write to a different cache block address
Non-WB write outside of	closes combining for previous writes. WB writes do not affect
	write combining. Only one line-sized buffer can be open for
current buffer
	write combining at a time. Once a buffer is closed for write
	combining, it cannot be reopened for write combining.
	Any IN/INS or OUT/OUTS instruction closes combining. The
I/O Read or Write	implied memory type for all IN/OUT instructions is UC,
	which cannot be combined.
	Any serializing instruction closes combining. These
Serializing instructions	instructions include: MOVCRx, MOVDRx, WRMSR, INVD,
	INVLPG, WBINVD, LGDT, LLDT, LIDT, LTR, CPUID, IRET, RSM,
	INIT, HALT.
Flushing instructions	Any flush instruction causes the WC to complete.
	Any instruction or processor operation that requires a cache
Locks	or bus lock closes write combining before starting the lock.
	Writes within a lock can be combined.
	A UC read closes write combining. A WC read closes
Uncacheable Read	combining only if a cache block address match occurs
	between the WC read and a write in the write buffer.
	Any WT write while write-combining for WC memory or any
Different memory type	WC write while write combining for WT memory closes write
	combining.
Buffer full	Write combining is closed if all 64 bytes of the write buffer
	are valid.
	If 16 processor clocks have passed since the most recent
WT time-out	write for WT write combining, write combining is closed.
	There is no time-out for WC write combining.
	Write combining is closed if a write fills the most significant
	byte of a quadword, which includes writes that are
WT write fills byte 7	misaligned across a quadword boundary. In the misaligned
	case, combining is closed by the LS part of the misaligned
	write and combining is opened by the MS part of the
	misaligned store.
	If a subsequent WT write is not in ascending sequential
WT Nonsequential	order, the write combining completes. WC writes have no
	addressing constraints within the 64-byte line being
	combined.
TLB AD bit set	Write combining is closed whenever a TLB reload sets the
	accessed (A) or dirty (D) bits of a Pde or Pte.

158 Write-Combining Operations