22007E/0 — November 1999

AMD Athlon™ Processor x86 Code Optimization

The initialization and start counters procedure sets the PerfEvtSel0 and/or PerfEvtSel1 MSRs for the events to be counted and the method used to count them and initializes the counter MSRs (PerfCtr[3:0]) to starting counts. The stop counters procedure stops the performance counters. (See “Starting and Stopping the Performance-Monitoring Counters” on page 168 for more information about starting and stopping the counters.)

The read counters procedure reads the values in the PerfCtr[3:0] MSRs, and a read time-stamp counter procedure reads the time-stamp counter. These procedures can be used instead of enabling the RDTSC and RDPMC instructions, which allow application code to read the counters directly.

Monitoring Counter Overflow

The AMD Athlon processor provides the option of generating a debug interrupt when a performance-monitoring counter overflows. This mechanism is enabled by setting the interrupt enable flag in one of the PerfEvtSel[3:0] MSRs. The primary use of this option is for statistical performance sampling.

To use this option, the operating system should do the following:

Provide an interrupt routine for handling the counter overflow as an APIC interrupt

Provide an entry in the IDT that points to a stub exception handler that returns without executing any instructions

Provide an event monitor driver that provides the actual interrupt handler and modifies the reserved IDT entry to point to its interrupt routine

When interrupted by a counter overflow, the interrupt handler needs to perform the following actions:

Save the instruction pointer (EIP register), code segment selector, TSS segment selector, counter values and other relevant information at the time of the interrupt

Reset the counter to its initial setting and return from the interrupt

Monitoring Counter Overflow

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AMD x86 manual Monitoring Counter Overflow