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AMD x86 manual Load-Store Unit LSU, Load/Store Unit

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AMD Athlon™ Processor x86 Code Optimization

22007E/0 — November 1999

Load-Store Unit (LSU)

The load-store unit (LSU) manages data load and store accesses to the L1 data cache and, if required, to the backside L2 cache or system memory. The 44-entry LSU provides a data interface for both the integer scheduler and the floating-point scheduler. It consists of two queues —a 12-entry queue for L1 cache load and store accesses and a 32-entry queue for L2 cache or system memory load and store accesses. The 12-entry queue can request a maximum of two L1 cache loads and two L1 cache (32-bits) stores per cycle. The 32-entry queue effectively holds requests that missed in the L1 cache probe by the 12-entry queue. Finally, the LSU ensures that the architectural load and store ordering rules are preserved (a requirement for x86 architecture compatibility).

Operand

Buses

Result Buses

from

Core

	LSU	Data	Cache
		2-way,
	44-Entry
		64Kbytes

Store Data

to BIU

Figure 4. Load/Store Unit

138	AMD Athlon™ Processor Microarchitecture

Image 154

AMD x86 manual Load-Store Unit LSU, Load/Store Unit

Contents

AMD AthlonTM Processor Trademarks Contents Instruction Decoding Optimizations Cache and Memory Optimizations Scheduling Optimizations Floating-Point Optimizations General x86 Optimization Guidelines 127 Appendix B Pipeline and Execution Unit Resources Overview Appendix E Programming the Mtrr and PAT List of Figures Xii List of Tables Xiv Revision History Xvi Introduction About this DocumentSource Level Optimizations. Describes optimizations that AMD Athlon Processor Family AMD Athlon Processor Microarchitecture Summary AMD Athlon Processor Microarchitecture Summary AMD Athlon Processor x86 Code Optimization Top Optimizations Group I Optimizations Essential Optimizations Memory Size and Alignment IssuesOptimization Star Use the 3DNow! Prefetch and Prefetchw InstructionsLoad-Execute Instruction Usage Group II Optimizations-Secondary OptimizationsSelect DirectPath Over VectorPath Instructions Use Load-Execute InstructionsUse 3DNow! Instructions Take Advantage of Write CombiningAvoid Branches Dependent on Random Data Avoid Placing Code and Data in the Same 64-Byte Cache Line 22007E/0 November Source Level Optimizations Use 32-Bit Data Types for Integer CodeExample 1 Avoid Consider the Sign of Integer OperandsExample Preferred Use unsigned types for Use Array Style Instead of Pointer Style CodeExample Avoid Use signed types forVertex Example 2 Preferred Completely Unroll Small Loops Avoid Unnecessary Store-to-Load DependenciesAvoid Unnecessary Store-to-Load Dependencies Consider Expression Order in Compound Branch Conditions Optimize Switch Statements Switch Statement UsageUse Prototypes for All Functions Generic Loop Hoisting Use Const Type QualifierExample Generalization for Multiple Constant Control Code Declare Local Functions as Static Dynamic Memory Allocation Consideration Introduce Explicit Parallelism into CodeExplicitly Extract Common Subexpressions Avoid Language Structure Component ConsiderationsExample PreferredOriginal ordering Avoid Sort Local Variables According to Base Type SizeNew ordering, with padding Preferred Accelerating Floating-Point Divides and Square Roots Improved ordering PreferredAccelerating Floating-Point Divides and Square Roots Avoid Unnecessary Integer Division AMD Athlon Processor x86 Code Optimization Instruction Decoding Optimizations OverviewLoad-Execute Instruction Usage Select DirectPath Over VectorPath InstructionsUse Load-Execute Integer Instructions TOP Align Branch Targets in Program Hot Spots Use Short Instruction LengthsAvoid Partial Register Reads and Writes Example 2 AvoidUse 8-Bit Sign-Extended Immediates Replace Certain Shld Instructions with Alternative CodeUse 8-Bit Sign-Extended Displacements Code Padding Using Neutral Code FillersRecommendations for the AMD Athlon Processor Code Padding Using Neutral Code Fillers AMD Athlon Processor x86 Code Optimization NOP6EDI AMD Athlon Processor x86 Code Optimization Cache and Memory Optimizations Memory Size and Alignment IssuesAvoid Memory Size Mismatches Align Data Where Possible Use the 3DNow! Prefetch and Prefetchw InstructionsExample Multiple Prefetches CodeMOV ECX, -LARGENUM Determining Prefetch Distance Prefetch Distance = 200 DS/C bytesTake Advantage of Write Combining Avoid Placing Code and Data in the Same 64-Byte Cache LineStore-to-Load Forwarding Restrictions Store-to-Load Forwarding Pitfalls -True DependenciesExample 3 Avoid Example 4 AvoidExample 6 Avoid Example 5 PreferredExample 7 Avoid Stack Alignment Considerations Summary of Store-to-Load Forwarding Pitfalls to AvoidAlign Tbyte Variables on Quadword Aligned Addresses Sort Variables According to Base Type Size Branch Optimizations Avoid Branches Dependent on Random DataAMD Athlon Processor Specific Code Blended AMD-K6and AMD Athlon Processor CodeExample 6 Increment Ring Buffer Offset Always Pair Call and ReturnExample 7 Integer Signum Function Replace Branches with Computation in 3DNow! Code Muxing ConstructsCode Sample Code Translated into 3DNow! Code3DNow! code MM5 Pfsub Psrad Avoid the Loop Instruction Avoid Far Control Transfer InstructionsAvoid Recursive Functions Unrolling Loops Scheduling OptimizationsSchedule Instructions According to their Latency Complete Loop UnrollingPartial Loop Unrolling Without Loop Unrolling With Partial Loop UnrollingUnrolled Loops Deriving LoopControl For Partially Example 1 rolled loopUse Function Inlining OverviewAvoid Address Generation Interlocks Always Inline Functions if Called from One SiteUse Movzx and Movsx Minimize Pointer Arithmetic in LoopsMOV ECX, Maxsize Push Memory Data Carefully Example 3 PreferredPush Memory Data Carefully Replace Divides with Multiplies Integer OptimizationsMultiplication by Reciprocal Division Utility Unsigned Division by Multiplication of Constant Simpler Code for Signed Division by Multiplication of ConstantRestricted Dividend Remainder of Signed Signed Division BySigned Division By 2n Integer 2 orUse Alternative Code When Multiplying by a Constant Integer 2n or -2nADD REG1, REG1 REG1, REG2 SHL Use MMX Instructions for Integer-Only Work Latency of Repeated String Instructions Repeated String Instruction UsageGuidelines for Repeated String Instructions Align Source Using MovqEnsure DF=0 UP Destination withUse XOR Instruction to Clear Integer Registers Efficient 64-Bit Integer ArithmeticExample 5 Right shift Example 4 Left shiftExample 6 Multiplication Example 7 Division EBX, ESP+12 DividendloExample 8 Remainder SHR EDX Efficient Implementation of Population Count Function StepBit field. Thus the following computation is performed MOV EDX, EDX SHR Derivation of Multiplier Used for Integer Division by Utility sdiv.exe was compiled using the following code MOV ECX EDX Imul ADD SHR SAR Ensure All FPU Data is Aligned Floating-Point OptimizationsUse Multiplies Rather than Divides Floating-Point Compare Instructions Use Ffreep Macro to Pop One Register from the FPU StackAvoid Using Extended-Precision Data Use the Fxch Instruction Rather than FST/FLD PairsMinimize Floating-Point-to-Integer Conversions Example 1 FastExample 2 Potentially faster Example 3 Potentially faster Example 4 FastestFloating-Point Subexpression Elimination 104 Take Advantage of the Fsincos Instruction 106 Use 3DNow! Instructions 3DNow! and MMX OptimizationsUse Femms Instruction Optimized 14-Bit Precision Divide Use 3DNow! Instructions for Fast DivisionOptimized Full 24-Bit Precision Divide Pipelined Pair of 24-Bit Precision Divides Newton-Raphson ReciprocalOptimized 15-Bit Precision Square Root Optimized 24-Bit Precision Square RootNewton-Raphson Reciprocal Square Root Specific Code 3DNow! and MMX Intra-Operand SwappingAMD Athlon Blended CodeFast Conversion of Signed Words to Floating-Point Use MMX Pxor to Negate 3DNow! DataPositive One Negative, One Use MMX Pcmp Instead of 3DNow! PfcmpBoth Numbers PositiveUse MMX Instructions for Block Copies and Block Fills AMD-K6and AMD Athlon Processor Blended Code116 Processor Specific Use MMX Pxor to Clear All Bits in an MMX Register Optimized Matrix Multiplication Use MMX Pcmpeqd to Set All Bits in an MMX RegisterMOV EBX, RES Optimized Matrix Multiplication 121 Data Use 3DNow! Pavgusb for MPEG-2 Motion Compensation MM0=QWORD1 Stream of Packed Unsigned Bytes Complex Number Arithmetic General x86 Optimization Guidelines Short FormsRegister Operands DependenciesStack Allocation AMD Athlon Processor Microarchitecture IntroductionAMD Athlon Processor Microarchitecture Superscalar ProcessorAMD Athlon Processor Microarchitecture 131 Predecode Branch PredictionEarly Decoding Instruction Control Unit Data CacheInteger Scheduler Integer Execution UnitFloating-Point Scheduler Floating-Point Execution Unit 12 toLoad-Store Unit LSU Load/Store UnitWrite Combining L2 Cache ControllerAMD Athlon System Bus 140 AMD Athlon Processor Microarchitecture Pipeline and Execution Unit Resources Overview Fetch and Decode Pipeline StagesC T L R O M Cycle 3 DirectPath Cycle 1-FETCHCycle 2-SCAN Cycle 3 VectorPathInteger Pipeline Stages Integer Pipeline StagesCycle 9-ADDGEN Cycle 7-SCHEDCycle 8-EXEC Cycle 10 -DCACCFloating-Point Pipeline Stages Floating-Point Pipeline StagesCycle 9-SCHEDW Cycle 7-STKRENCycle 8-REGREN Cycle 10 -SCHEDOperands Execution Unit ResourcesTerminology ResultsInteger Pipeline Operation Types Integer Pipeline OperationsInteger Decode Types Floating-Point Pipeline Operation Types Floating-Point Pipeline OperationsFloating-Point Decode Types Load/Store Unit Stages Load/Store Pipeline OperationsStage 1 Cycle Stage 2 Cycle Stage 3 Cycle Code Sample Analysis ADD EDI, EBX SHL Imul EAX, ECX INC ESI MOVINC EBX ADD ESI, EDX DEC EDX MOV EDI, ECX SUB Sample 2 Integer Register and Memory Load OperationsSAR Appendix C Implementation Write CombiningWrite-Combining Definitions and Abbreviations What is Write Combining?Programming Details Write-Combining Operations Write Combining Completion Events INIT, HaltAMD Athlon System Bus Commands Generation Rules Sending Write-Buffer Data to the System160 Write-Combining Operations Performance-Monitoring Counters Performance Counter UsagePerfEvtSel30 MSRs MSR Addresses C0010000h-C0010003h PerfEvtSel30 RegistersPerformance Counter Usage 163 Performance-Monitoring Counters Snoop hits 65h73h 74hInstruction cache fetches Event Source Event DescriptionWaited to use the L2 Instruction cache missesPerfCtr30 MSRs MSR Addresses C0010004h-C0010007h Event and Time-Stamp Monitoring Software Starting and Stopping the Performance-Monitoring CountersMonitoring Counter Overflow 170 Monitoring Counter Overflow Programming the Mtrr Memory Type Range Register Mtrr Mechanism172 Memory Type Range Register Mtrr Mechanism FFFFFFFFh Fixed Ranges100000h Kbytes each Fixed Ranges C0000h 80000h Mtrr Capability Memory TypesMemory Type Encodings Register FormatMemory Type Range Register Mtrr Mechanism 175 Standard Mtrr Types and Properties Attribute Table PAT Attribute Table MSR 277hMTRRs and PAT PAT Entry Reset ValuePATi 3-Bit Encodings PATiEffective Memory Type Based on PAT and MTRRs PAT Memory Type Mtrr Memory TypeFinal Output Memory Types Input Memory TypeAttribute Table PAT 181 Bffff Bbfff B7FFF B3FFF Affff Abfff A7FFF A3FFF 7FFFF 6FFFF 5FFFF 4FFFF 3FFFF 2FFFF 1FFFF 0FFFF9FFFF 9BFFF 97FFF 93FFF 8FFFF 8BFFF 87FFF 83FFF C7FFF C6FFF C5FFF C4FFF C3FFF C2FFF C1FFF C0FFFAttribute Table PAT 183 MTRRphysMaskn Register Format MTRR-Related Model-Specific Register MSR Map 186 Appendix F Instruction Dispatch Execution ResourcesAAD Integer InstructionsAAA AAMADC mem8, reg8 ModR/M Decode ByteADC mreg8, reg8 ADC mreg16/32, reg16/32Bswap ECX BoundBswap EAX Bswap EDXCLD CBW/CWDECLC CLICMOVG/CMOVNLE reg16/32, reg16/32 0Fh CMOVE/CMOVZ reg16/32, reg16/32 0FhCMOVE/CMOVZ reg16/32, mem16/32 0Fh CMOVG/CMOVNLE reg16/32, mem16/32 0FhDAA CpuidCWD/CDQ DASAX, DX EnterAL, DX EAX, DXInvd InvlpgLahf LeaveLSL reg16/32, mreg16/32 0Fh 03h LOOPE/LOOPZ disp8 E1hLOOPNE/LOOPNZ disp8 E0h LSL reg16/32, mem16/32 0Fh 03hNOP Xchg EAX, EAX OUT DX, EAX OUT DX, ALOUT DX, AX POP ESPOP EBP POP EBXPOP ESP POP ESIRdpmc RdmsrRdtsc Sahf SBB reg8, mreg8 SBB mreg16/32, reg16/32SBB mem16/32, reg16/32 SBB reg8, mem8Setns mreg8 Sets mreg8Sets mem8 Setns mem8STD STCSTI Sysexit SyscallSysenter SysretXchg EAX, EDX Xchg EAX, EAXXchg EAX, ECX Xchg EAX, EBXMMX Instructions EmmsPandn mmreg, mem64 Pandn mmreg1, mmreg2DFh Pcmpeqb mmreg1, mmreg2FADD/FMUL MMX Extensions FPUFloating-Point Instructions Fcos FcomppFdecstp Finit FincstpFLD1 FLDLG2 FLDL2EFLDL2T FLDLN2Fucom Fstsw AXFtst FucompDNow! Instructions FemmsDNow! Extensions DirectPath versus VectorPath Instructions DirectPath InstructionsBT mreg16/32, reg16/32 BT mreg16/32, imm8 BT mem16/32, imm8 DirectPath Integer InstructionsCBW/CWDE CLC CMC DEC mreg8 DEC mem8 DEC mreg16/32 DEC mem16/32 INC mreg8 INC mem8 INC mreg16/32 INC mem16/32 JO short disp8222 DirectPath Instructions DirectPath Instructions 223 224 DirectPath Instructions Wait Xchg EAX, EAX 226 DirectPath Instructions DirectPath MMX Instructions DirectPath MMX Extensions Fist mem16int DirectPath Floating-Point InstructionsFcompp Fdecstp FLD1 FLDL2E FLDL2T FLDLG2 FLDLN2 Fldpi FldzFtst Fucom Fucomp Fucompp Fwait Fxch AAA AAD AAM AAS VectorPath InstructionsVectorPath Integer Instructions CLD CLI CltsInstruction Mnemonic DIV EAX, mem16/32 AL, DX AX, DX EAX, DX Invd InvlpgPUSHA/PUSHAD PUSHF/PUSHFD POP mreg 16/32 POP mem 16/32Push mreg16/32 Push mem16/32 Rdmsr Rdpmc RdtscSyscall Sysenter Sysexit Sysret VectorPath MMX InstructionsVectorPath MMX Extensions Wbinvd WrmsrFscale Fsin Fsincos VectorPath Floating-Point InstructionsFptan Fpatan Frndint Fxam Fxtract FYL2X FYL2XP1236 Index 238 Index Index 239 240 Index