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Analog Devices ADSP-2186 specifications Parameter Min Max Unit Idma Address Latch

Models: ADSP-2186

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					ADSP-2186


Parameter			Min	Max		Unit

IDMA Address Latch
Timing Requirements:
tIALP	Duration of Address Latch1, 3		10			ns
tIASU	IAD15–0 Address Setup before Address Latch End3		5			ns
tIAH	IAD15–0 Address Hold after Address Latch End3		2			ns
tIKA	IACK	Low before Start of Address Latch2, 3	0			ns
tIALS	Start of Write or Read after Address Latch End2, 3		3			ns

NOTES

1Start of Address Latch = IS Low and IAL High.

2Start of Write or Read = IS Low and IWR Low or IRD Low.

3End of Address Latch = IS High or IAL Low.

IACK

IAL

IAD 15–0

IRD OR

IWR

tIKA

tIALP

tIASU

tIAH

tIALS

Figure 20. IDMA Address Latch

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Analog Devices ADSP-2186 specifications Parameter Min Max Unit Idma Address Latch

Contents

General Description Functional Block DiagramGeneral Note Architecture Overview Development SystemAdditional Information PIN Descriptions Serial PortsSetting Memory Mode Input Pin Name Pins Output FunctionCommon-Mode Pins Memory Interface PinsInterrupts LOW Power OperationPower-Down Source Of Interrupt Interrupt Vector Address HexSystem Interface Idle nIdle Slow IdleProgram Memory Clock SignalsReset Memory ArchitectureData Memory Space Full Memory ModeMemory A13 A120 Address Range Wait State RegisterMemory Space Word Size Alignment Byte Memory DMA BDMA, Full Memory ModeInternal Memory DMA Port Idma Port Host Memory Mode InternalBooting Method Designing AN EZ-ICE*-COMPATIBLE System MR Value Biased Unbiased Before RND RND ResultSyntax IOaddr = dreg dreg = IOaddr Biased RoundingPM, DM, BM, IOM, & CM Target Board Connector for EZ-ICE* ProbeTarget System Interface Signals Target Memory InterfaceGrades Parameter Test Conditions Min Typ Max Unit Grade Parameter Min Max UnitWR Low Assumptions Total Power Dissipation = Pint + C × VDD2 × fPower Dissipation PackageTest Conditions Output Disable TimeOutput Enable Time Capacitive LoadingControl Signals Parameter Min Max Clock Signals and ResetFlag Output Hold after Clkout Low5 25 tCK IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Flag Output Delay from Clkout Low5 TCK + Parameter Min Max Unit Interrupts and FlagParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Duration of Write1 IAD15-0 Data Setup before End of Write2, 3Parameter Min Max Idma Write, Short Write Cycle Iack Low before Start of Write1Low4 TCK IAD15-0 Data Setup beforeParameter Min Max Unit Idma Write, Long Write Cycle Low before Start of Write1Parameter Min Max Unit Idma Read, Long Read Cycle High after Start of Read1 Duration of Read Switching CharacteristicsParameter Min Max Unit Idma Read, Short Read Cycle ADSP-2186 Lead Tqfp Package PinoutA6/IAD5 PinNumber Name A4/IAD3 A5/IAD4ST-100 Outline DimensionsOrdering Guide Page C2999-6-3/97

ADSP-2186

Parameter

Min

Max

Unit

IDMA Address Latch

IACK

Start of Write or Read after Address Latch End2, 3

Figure 20. IDMA Address Latch

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