Manuals / Analog Devices / Computer Equipment / Computer Hardware

Analog Devices ADSP-2186 Parameter Min Max Idma Write, Short Write Cycle, Duration of Write1

Models: ADSP-2186

1 32

Download 32 pages 39.75 Kb

Page 24

ADSP-2186

TIMING PARAMETERS

Parameter				Min	Max
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW	IACK Low before Start of Write1			0
tIWP	Duration of Write1, 2			15
tIDSU	IAD15–0 Data Setup before End of Write2, 3, 4			5
tIDH	IAD15–0 Data Hold after End of Write2, 3, 4			2
Switching Characteristics:
tIKHW	Start of Write to	IACK	High		15

NOTES

1Start of Write = IS Low and IWR Low.

2End of Write = IS High or IWR High.

3If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH. 4If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.

Unit

ns ns ns ns

ns

tIKW

IACK

IS

IWR

tIKHW

tIWP

tIDSU

tIDH

IAD 15–0

DATA

Figure 21. IDMA Write, Short Write Cycle

–24–

REV. 0

Image 24

Analog Devices ADSP-2186 specifications Parameter Min Max Idma Write, Short Write Cycle, Iack Low before Start of Write1

Contents

Functional Block Diagram General NoteGeneral Description Development System Additional InformationArchitecture Overview Serial Ports PIN Descriptions Input Pin Name Pins Output Function Common-Mode PinsMemory Interface Pins Setting Memory Mode LOW Power Operation Power-DownSource Of Interrupt Interrupt Vector Address Hex Interrupts Idle n IdleSlow Idle System Interface Clock Signals ResetMemory Architecture Program Memory Space Full Memory Mode Memory A13 A120Address Range Wait State Register Data Memory Byte Memory DMA BDMA, Full Memory Mode Internal Memory DMA Port Idma Port Host Memory ModeInternal Memory Space Word Size Alignment Booting Method MR Value Biased Unbiased Before RND RND Result Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Designing AN EZ-ICE*-COMPATIBLE System Target Board Connector for EZ-ICE* Probe Target System Interface SignalsTarget Memory Interface PM, DM, BM, IOM, & CM Grade Parameter Min Max Unit Grades Parameter Test Conditions Min Typ Max Unit WR Low Total Power Dissipation = Pint + C × VDD2 × f Power DissipationPackage Assumptions Output Disable Time Output Enable TimeCapacitive Loading Test Conditions Parameter Min Max Clock Signals and Reset Control Signals IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK + Flag Output Delay from Clkout Low5 TCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 25 tCK Parameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch IAD15-0 Data Setup before End of Write2, 3 Parameter Min Max Idma Write, Short Write CycleIack Low before Start of Write1 Duration of Write1 IAD15-0 Data Setup before Parameter Min Max Unit Idma Write, Long Write CycleLow before Start of Write1 Low4 TCK Parameter Min Max Unit Idma Read, Long Read Cycle Duration of Read Switching Characteristics Parameter Min Max Unit Idma Read, Short Read CycleHigh after Start of Read1 Lead Tqfp Package Pinout ADSP-2186 Pin Number Name A4/IAD3A5/IAD4 A6/IAD5 Outline Dimensions Ordering GuideST-100 Page C2999-6-3/97