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Analog Devices ADSP-2186 specifications Parameter Min Max Unit Interrupts and Flag

Models: ADSP-2186

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ADSP-2186

TIMING PARAMETERS

Parameter			Min	Max	Unit

Interrupts and Flag
Timing Requirements:
tIFS	IRQx	, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4	0.25 tCK + 15		ns
tIFH	IRQx	, FI, or PFx Hold after CLKOUT High1, 2, 3, 4	0.25 tCK		ns
Switching Characteristics:
tFOH	Flag Output Hold after CLKOUT Low5		0.25 tCK – 7		ns
tFOD	Flag Output Delay from CLKOUT Low5			0.5 tCK + 5	ns

NOTES

1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.)

2Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

5Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.

CLKOUT

FLAG OUTPUTS

IRQx

FI

PFx

tFOD

tFOH

tIFH

tIFS

Figure 15. Interrupts and Flags

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Analog Devices ADSP-2186 Parameter Min Max Unit Interrupts and Flag, IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +

Contents

Functional Block Diagram General NoteGeneral Description Development System Additional InformationArchitecture Overview Serial Ports PIN Descriptions Memory Interface Pins Input Pin Name Pins Output FunctionCommon-Mode Pins Setting Memory Mode Source Of Interrupt Interrupt Vector Address Hex LOW Power OperationPower-Down Interrupts Slow Idle Idle nIdle System Interface Memory Architecture Clock SignalsReset Program Memory Address Range Wait State Register Space Full Memory ModeMemory A13 A120 Data Memory Internal Byte Memory DMA BDMA, Full Memory ModeInternal Memory DMA Port Idma Port Host Memory Mode Memory Space Word Size Alignment Booting Method Biased Rounding MR Value Biased Unbiased Before RND RND ResultSyntax IOaddr = dreg dreg = IOaddr Designing AN EZ-ICE*-COMPATIBLE System Target Memory Interface Target Board Connector for EZ-ICE* ProbeTarget System Interface Signals PM, DM, BM, IOM, & CM Grade Parameter Min Max Unit Grades Parameter Test Conditions Min Typ Max Unit WR Low Package Total Power Dissipation = Pint + C × VDD2 × fPower Dissipation Assumptions Capacitive Loading Output Disable TimeOutput Enable Time Test Conditions Parameter Min Max Clock Signals and Reset Control Signals Parameter Min Max Unit Interrupts and Flag IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Flag Output Delay from Clkout Low5 TCK + Flag Output Hold after Clkout Low5 25 tCK Parameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Iack Low before Start of Write1 IAD15-0 Data Setup before End of Write2, 3Parameter Min Max Idma Write, Short Write Cycle Duration of Write1 Low before Start of Write1 IAD15-0 Data Setup beforeParameter Min Max Unit Idma Write, Long Write Cycle Low4 TCK Parameter Min Max Unit Idma Read, Long Read Cycle Duration of Read Switching Characteristics Parameter Min Max Unit Idma Read, Short Read CycleHigh after Start of Read1 Lead Tqfp Package Pinout ADSP-2186 A5/IAD4 PinNumber Name A4/IAD3 A6/IAD5 Outline Dimensions Ordering GuideST-100 Page C2999-6-3/97