Manuals / Analog Devices / Computer Equipment / Computer Hardware

Analog Devices ADSP-2186 specifications Parameter Min Max Unit Memory Write

Models: ADSP-2186

1 32

Download 32 pages 39.75 Kb

Page 21

Image 21

ADSP-2186

Parameter

Min

Max

Unit

Memory Write

Switching Characteristics:

tDW

Data Setup before

High

0.5 tCK – 7+ w

tDH

Data Hold after WR High

0.25 tCK – 2

tWP

Pulse Width

0.5 tCK – 5 + w

tWDE

Low to Data Enabled

tASW

A0-A13,

xMS

Setup before

Low

0.25 tCK – 6

tDDR

Data Disable before

Low

0.25 tCK – 7

tCWR

CLKOUT High to

Low

0.25 tCK – 5

0.25 tCK + 7

tAW

A0-A13, xMS, Setup before

Deasserted

0.75 tCK – 9 + w

tWRA

A0-A13,

xMS

Hold after

Deasserted

0.25 tCK – 3

tWWR

High to

Low

0.5 tCK – 5

w = wait states × tCK.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

tASW

tCWR

	tWRA
	tWP	tWWR
tAW	tDH	tDDR
	tDH	tDDR

tDW tWDE

Figure 18. Memory Write

REV. 0

–21–

Page 21

Image 21

Analog Devices ADSP-2186 specifications Parameter Min Max Unit Memory Write

Contents

Functional Block Diagram General NoteGeneral Description Development System Additional InformationArchitecture Overview PIN Descriptions Serial Ports Common-Mode Pins Input Pin Name Pins Output FunctionMemory Interface Pins Setting Memory Mode Power-Down LOW Power OperationSource Of Interrupt Interrupt Vector Address Hex Interrupts Idle Idle nSlow Idle System Interface Reset Clock SignalsMemory Architecture Program Memory Memory A13 A120 Space Full Memory ModeAddress Range Wait State Register Data Memory Internal Memory DMA Port Idma Port Host Memory Mode Byte Memory DMA BDMA, Full Memory ModeInternal Memory Space Word Size Alignment Booting Method Syntax IOaddr = dreg dreg = IOaddr MR Value Biased Unbiased Before RND RND ResultBiased Rounding Designing AN EZ-ICE*-COMPATIBLE System Target System Interface Signals Target Board Connector for EZ-ICE* ProbeTarget Memory Interface PM, DM, BM, IOM, & CM Grades Parameter Test Conditions Min Typ Max Unit Grade Parameter Min Max Unit WR Low Power Dissipation Total Power Dissipation = Pint + C × VDD2 × fPackage Assumptions Output Enable Time Output Disable TimeCapacitive Loading Test Conditions Control Signals Parameter Min Max Clock Signals and Reset Flag Output Delay from Clkout Low5 TCK + IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 25 tCK Parameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle IAD15-0 Data Setup before End of Write2, 3Iack Low before Start of Write1 Duration of Write1 Parameter Min Max Unit Idma Write, Long Write Cycle IAD15-0 Data Setup beforeLow before Start of Write1 Low4 TCK Parameter Min Max Unit Idma Read, Long Read Cycle Duration of Read Switching Characteristics Parameter Min Max Unit Idma Read, Short Read CycleHigh after Start of Read1 ADSP-2186 Lead Tqfp Package Pinout Number Name A4/IAD3 PinA5/IAD4 A6/IAD5 Outline Dimensions Ordering GuideST-100 Page C2999-6-3/97