Analog Devices ADSP-2186 specifications Functional Block Diagram, General Note

a

DSP Microcomputer

ADSP-2186

FEATURES PERFORMANCE

FUNCTIONAL BLOCK DIAGRAM

30 ns Instruction Cycle Time 33 MIPS Sustained Performance

Single-Cycle Instruction Execution Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction Set Extensions

40K Bytes of On-Chip RAM, Configured as

					POWER-DOWN
					CONTROL
DATA ADDRESS					MEMORY		PROGRAMMABLE
							I/O
	GENERATORS		PROGRAM	8K 24		8K 16	AND
			SEQUENCER	PROGRAM		DATA
	DAG 1	DAG 2		MEMORY		MEMORY	FLAGS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

ARITHMETIC UNITS			SERIAL PORTS		TIMER
ALU	MAC	SHIFTER	SPORT 0	SPORT 1

ADSP-2100 BASE

ARCHITECTURE

FULL MEMORY

MODE

EXTERNAL ADDRESS

BUS

EXTERNAL DATA BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL DATA BUS

INTERNAL

DMA

PORT

HOST MODE

8K Words On-Chip Program Memory RAM and

8K Words On-Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction and Data Storage

Independent ALU, Multiplier/Accumulator and Barrel Shifter Computational Units

Two Independent Data Address Generators Powerful Program Sequencer Provides

Zero Overhead Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler 100-Lead TQFP

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to On-Chip Memory (Mode Selectable)

4 MByte Byte Memory Interface for Storage of Data Tables & Program Overlays

8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design

(Mode Selectable)

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port

*ICE-Port is a trademark of Analog Devices, Inc.

All trademarks are the property of their respective holders.

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Six External Interrupts

13 Programmable Flag Pins Provide Flexible System Signaling

UART Emulation through Software SPORT Reconfiguration ICE-Port™* Emulator Interface Supports Debugging

in Final Systems

GENERAL NOTE

This data sheet represents production grade specifications for the ADSP-2186 (5 V) processor. This data sheet also contains preliminary (x-grade) specifications for the new ADSP-2186 40 MHz processor.

GENERAL DESCRIPTION

The ADSP-2186 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The ADSP-2186 combines the ADSP-2100 family base archi- tecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory.

The ADSP-2186 integrates 40K bytes of on-chip memory con- figured as 8K words (24-bit) of program RAM and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equip- ment. The ADSP-2186 is available in 100-pin TQFP package.

In addition, the ADSP-2186 supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (x squared),

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