Ordering Guide, Outline Dimensions | Analog Devices ADSP-2186

ADSP-2186

ORDERING GUIDE

	Ambient	Instruction
	Temperature	Rate	Package	Package
Part Number	Range	(MHz)	Description	Option*
ADSP-2186KST-115	0°C to +70°C	28.8	100-Lead TQFP	ST-100
ADSP-2186BST-115	–40°C to +85°C	28.8	100-Lead TQFP	ST-100
ADSP-2186KST-133	0°C to +70°C	33.3	100-Lead TQFP	ST-100
ADSP-2186BST-133	–40°C to +85°C	33.3	100-Lead TQFP	ST-100
ADSP-2186KST-160x	0°C to +70°C	40.0	100-Lead TQFP	ST-100
ADSP-2186BST-160x	–40°C to +85°C	40.0	100-Lead TQFP	ST-100

*ST = Plastic Thin Quad Flatpack (TQFP).

OUTLINE DIMENSIONS

Dimensions shown in mm and (inches).

100-Lead Metric Thin Plastic Quad Flatpack (TQFP)

(ST-100)

			0.640	(16.25)
			0.630	(16.00) TYP SQ
			0.620	(15.75)
			0.555	(14.05)
			0.551	(14.00) TYP SQ
			0.547	(13.90)
			0.476	(12.10)
	0.063 (1.60) MAX		0.474	(12.05) TYP SQ
	0.063 (1.60) MAX		0.472	(12.00)
	0.024 (0.75)		0.472	(12.00)
	0.024 (0.75)
	0.022 (0.60) TYP	12°	100
	0.020 (0.50)		100
	0.020 (0.50)		1
		TYP
	SEATING
	PLANE
			TOP VIEW
			(PINS DOWN)

76

75

0.004

(0.102) MAX LEAD COPLANARITY

0° – 10°

	25
6° ± 4°	26
6° ± 4°

0.007	(0.177)	0.020 (0.50)
0.005	(0.127) TYP	BSC
0.005	(0.127) TYP
0.003	(0.077)	LEAD PITCH
		LEAD PITCH

51

50

0.010 (0.27)

0.009 (0.22) TYP

0.006 (0.17)

LEAD WIDTH

–30–

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Image 30

Analog Devices ADSP-2186 specifications Ordering Guide, Outline Dimensions, ST-100

Contents

Functional Block Diagram General NoteGeneral Description Development System Additional InformationArchitecture Overview Serial Ports PIN Descriptions Memory Interface Pins Input Pin Name Pins Output FunctionCommon-Mode Pins Setting Memory Mode Source Of Interrupt Interrupt Vector Address Hex LOW Power OperationPower-Down Interrupts Slow Idle Idle nIdle System Interface Memory Architecture Clock SignalsReset Program Memory Address Range Wait State Register Space Full Memory ModeMemory A13 A120 Data Memory Internal Byte Memory DMA BDMA, Full Memory ModeInternal Memory DMA Port Idma Port Host Memory Mode Memory Space Word Size Alignment Booting Method Biased Rounding MR Value Biased Unbiased Before RND RND ResultSyntax IOaddr = dreg dreg = IOaddr Designing AN EZ-ICE*-COMPATIBLE System Target Memory Interface Target Board Connector for EZ-ICE* ProbeTarget System Interface Signals PM, DM, BM, IOM, & CM Grade Parameter Min Max Unit Grades Parameter Test Conditions Min Typ Max Unit WR Low Package Total Power Dissipation = Pint + C × VDD2 × fPower Dissipation Assumptions Capacitive Loading Output Disable TimeOutput Enable Time Test Conditions Parameter Min Max Clock Signals and Reset Control Signals Parameter Min Max Unit Interrupts and Flag IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Flag Output Delay from Clkout Low5 TCK + Flag Output Hold after Clkout Low5 25 tCK Parameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Iack Low before Start of Write1 IAD15-0 Data Setup before End of Write2, 3Parameter Min Max Idma Write, Short Write Cycle Duration of Write1 Low before Start of Write1 IAD15-0 Data Setup beforeParameter Min Max Unit Idma Write, Long Write Cycle Low4 TCK Parameter Min Max Unit Idma Read, Long Read Cycle Duration of Read Switching Characteristics Parameter Min Max Unit Idma Read, Short Read CycleHigh after Start of Read1 Lead Tqfp Package Pinout ADSP-2186 A5/IAD4 PinNumber Name A4/IAD3 A6/IAD5 Outline Dimensions Ordering GuideST-100 Page C2999-6-3/97