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Analog Devices ADSP-2186 specifications Parameter Min Max Unit Idma Read, Short Read Cycle

Models: ADSP-2186

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ADSP-2186

Parameter			Min	Max	Unit

IDMA Read, Short Read Cycle
Timing Requirements:
tIKR	IACK	Low before Start of Read1	0		ns
tIRP	Duration of Read		15		ns
Switching Characteristics:
tIKHR	IACK	High after Start of Read1		15	ns
tIKDH	IAD15–0 Data Hold after End of Read2		0		ns
tIKDD	IAD15–0 Data Disabled after End of Read2			10	ns
tIRDE	IAD15–0 Previous Data Enabled after Start of Read		0		ns
tIRDV	IAD15–0 Previous Data Valid after Start of Read			15	ns

NOTES

1Start of Read = IS Low and IRD Low.

2End of Read = IS High or IRD High.

IACK

tIKR

tIKHR

IRD

tIRDE

IAD 15–0

tIRDV

tIRP

DATA

tIKDH

tIKDD

Figure 24. IDMA Read, Short Read Cycle

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Analog Devices ADSP-2186 Parameter Min Max Unit Idma Read, Short Read Cycle, Duration of Read Switching Characteristics

Contents

Functional Block Diagram General NoteGeneral Description Development System Additional InformationArchitecture Overview PIN Descriptions Serial PortsSetting Memory Mode Input Pin Name Pins Output FunctionCommon-Mode Pins Memory Interface PinsInterrupts LOW Power OperationPower-Down Source Of Interrupt Interrupt Vector Address HexSystem Interface Idle nIdle Slow IdleProgram Memory Clock SignalsReset Memory ArchitectureData Memory Space Full Memory ModeMemory A13 A120 Address Range Wait State RegisterMemory Space Word Size Alignment Byte Memory DMA BDMA, Full Memory ModeInternal Memory DMA Port Idma Port Host Memory Mode InternalBooting Method Designing AN EZ-ICE*-COMPATIBLE System MR Value Biased Unbiased Before RND RND ResultSyntax IOaddr = dreg dreg = IOaddr Biased RoundingPM, DM, BM, IOM, & CM Target Board Connector for EZ-ICE* ProbeTarget System Interface Signals Target Memory InterfaceGrades Parameter Test Conditions Min Typ Max Unit Grade Parameter Min Max UnitWR Low Assumptions Total Power Dissipation = Pint + C × VDD2 × fPower Dissipation PackageTest Conditions Output Disable TimeOutput Enable Time Capacitive LoadingControl Signals Parameter Min Max Clock Signals and ResetFlag Output Hold after Clkout Low5 25 tCK IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Flag Output Delay from Clkout Low5 TCK + Parameter Min Max Unit Interrupts and FlagParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Duration of Write1 IAD15-0 Data Setup before End of Write2, 3Parameter Min Max Idma Write, Short Write Cycle Iack Low before Start of Write1Low4 TCK IAD15-0 Data Setup beforeParameter Min Max Unit Idma Write, Long Write Cycle Low before Start of Write1Parameter Min Max Unit Idma Read, Long Read Cycle Duration of Read Switching Characteristics Parameter Min Max Unit Idma Read, Short Read CycleHigh after Start of Read1 ADSP-2186 Lead Tqfp Package PinoutA6/IAD5 PinNumber Name A4/IAD3 A5/IAD4Outline Dimensions Ordering GuideST-100 Page C2999-6-3/97

ADSP-2186

Parameter

Min

Max

Unit

IDMA Read, Short Read Cycle

IACK

Duration of Read

Switching Characteristics:

IACK

High after Start of Read1

Figure 24. IDMA Read, Short Read Cycle

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