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Analog Devices ADSP-2186 Parameter Min Max Unit Idma Write, Long Write Cycle, Low4 TCK

Models: ADSP-2186

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									ADSP-2186


Parameter							Min	Max		Unit

IDMA Write, Long Write Cycle
Timing Requirements:
tIKW	IACK	Low before Start of Write1					0			ns
tIKSU	IAD15–0 Data Setup before				IACK	Low2, 3, 4	0.5 tCK + 10			ns
tIKH	IAD15–0 Data Hold after IACK Low2, 3, 4						2			ns
Switching Characteristics:
tIKLW	Start of Write to		IACK	Low4			1.5 tCK			ns
tIKHW	Start of Write to IACK High							15		ns

NOTES

1Start of Write = IS Low and IWR Low.

2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.

3If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.

4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

tIKW

IACK

IWR

tIKHW

tIKLW

tIKSU tIKH

IAD 15–0

DATA

Figure 22. IDMA Write, Long Write Cycle

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Analog Devices ADSP-2186 Parameter Min Max Unit Idma Write, Long Write Cycle, Low before Start of Write1, Low4 TCK

Contents

General Note Functional Block DiagramGeneral Description Additional Information Development SystemArchitecture Overview PIN Descriptions Serial PortsCommon-Mode Pins Input Pin Name Pins Output FunctionMemory Interface Pins Setting Memory ModePower-Down LOW Power OperationSource Of Interrupt Interrupt Vector Address Hex InterruptsIdle Idle nSlow Idle System InterfaceReset Clock SignalsMemory Architecture Program MemoryMemory A13 A120 Space Full Memory ModeAddress Range Wait State Register Data MemoryInternal Memory DMA Port Idma Port Host Memory Mode Byte Memory DMA BDMA, Full Memory ModeInternal Memory Space Word Size AlignmentBooting Method Syntax IOaddr = dreg dreg = IOaddr MR Value Biased Unbiased Before RND RND ResultBiased Rounding Designing AN EZ-ICE*-COMPATIBLE SystemTarget System Interface Signals Target Board Connector for EZ-ICE* ProbeTarget Memory Interface PM, DM, BM, IOM, & CMGrades Parameter Test Conditions Min Typ Max Unit Grade Parameter Min Max UnitWR Low Power Dissipation Total Power Dissipation = Pint + C × VDD2 × fPackage AssumptionsOutput Enable Time Output Disable TimeCapacitive Loading Test ConditionsControl Signals Parameter Min Max Clock Signals and ResetFlag Output Delay from Clkout Low5 TCK + IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 25 tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle IAD15-0 Data Setup before End of Write2, 3Iack Low before Start of Write1 Duration of Write1Parameter Min Max Unit Idma Write, Long Write Cycle IAD15-0 Data Setup beforeLow before Start of Write1 Low4 TCKParameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Short Read Cycle Duration of Read Switching CharacteristicsHigh after Start of Read1 ADSP-2186 Lead Tqfp Package PinoutNumber Name A4/IAD3 PinA5/IAD4 A6/IAD5Ordering Guide Outline DimensionsST-100 Page C2999-6-3/97

ADSP-2186

Parameter

Min

Max

Unit

IDMA Write, Long Write Cycle

IACK

Low before Start of Write1

IAD15–0 Data Setup before

IACK

Start of Write to

IACK

Low4

1.5 tCK

Start of Write to IACK High

Figure 22. IDMA Write, Long Write Cycle

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