Brother HL-1020, HL-1040 Asic HL-820/1020/1040, Nmi, Fifo, Scanint Cdcc / Boise / Data Extension

1.3.2ASIC

HL-820/1020/1040

The ASIC is composed of a Cell Based IC that contains the following functional blocks.

(1)Oscillator circuit

Generates the main clock for the CPU by dividing the source clock frequency into two.

(2)Address decoder

Generates the CS for each device.

(3)DRAM control

Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls refresh processing (CAS before RAS self-refreshing method).

(4)Interrupt control

Interrupt levels:

Priority High 7 NMI

6 FIFO

5EXINT(Option Serial I/O)

4BD / Timer 1

3 SCANINT

2 CDCC / BOISE / DATA EXTENSION

Low 1 Timer 2

(5)Timers

The following timers are incorporated:

Timer 1	16-bit timer
Timer 2	10-bit timer
Timer 3	Watch-dog timer

(6)FIFO

A 5,120-bit FIFO is incorporated. Data for one raster scan is transferred from the RAM to the FIFO by DMA transmission and is output as serial video data. The data cycle is 10.22 MHz.

(7)CDCC parallel I/O <Data receiving>

There are two modes in this unit. One is the CPU receiving mode and the other is the DMA receiving mode. In the CPU receiving mode the CPU receives the command data from the PC, and after the CPU is switched to the DMA mode, it receives the image data and writes to the DRAM directly.

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