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Cisco ONS 15454 Reference Manual, R8.5.x
78-18106-01
Chapter 2 Common Control Cards
2.3.1 TCC2P Functionality
reference as the system-timing reference. You can provision any of the clock input s as primary or
secondary timing sources. A slow-reference tracking loop allows the TCC2P card to synchronize with
the recovered clock, which provides holdover if the reference is lost.
The minimum free-run accuracy, holdover stability, pull-in, and hold-in characteristics are as defined in
ITU-T G.813 option I in Section 5, 6, and 10, ITU-T G.811 Section 5, and ITU-T G.812 Sections 6 and
7, as well as in ANSI EN 300 462-5-1.
Note If SDH timing is selected (see the “2.3.1.1.2 SDH Timing Operation” section on page 2-13), it is not
possible to select an E1 or DS1 port from the DS1/E1-56 high-density card as a timing referenc e.
2.3.1.1.1 SONET Timing Operation
The TCC2P card supports a 64 kHz + 8 kHz composite clock BITS input (BI TS IN) as well as a
6.312-MHz BITS OUT clock. The BITS clock on the system is configurable as DS1 (default),
1.544 MHz, or 64 kHz. The BITS O UT clock runs at a rate determined by the BITS I N clock, as follows:
• If BITS IN = DS1, then BITS OUT = DS1 (default)
• If BITS IN = 1.544 MHz (square wave clock), then BITS OUT = 1.544 MHz (square wave clock)
• If BITS IN = 64 kHz, then BITS OUT = 6.312 MHz or DS 1
A BITS output interface configured as 6.312 MHz complies with ITU-T G.703, Appendix II, Table II.4,
with a monitor level of –40 dBm +/– 4 dBm.
2.3.1.1.2 SDH Timing Operation
The TCC2P card supports typical external E1 SDH timing sources so that the card can be provisioned to
accept either an SDH or SONET timing standard. The initial default is for the card to use SONET timing;
the default can be changed to SDH timing after the TCC2P card boots up. The BITS OUT clock runs at
a rate determined by the BITS IN clock, as follows:
• If BITS IN = E1, then BITS OUT = E1
• If BITS IN = 2.048 MHz (square wave clock), then BITS OUT = 2.048 MHz (square wave clock)
• If BITS IN = 64 kHz, then BITS OUT = 6.312 MHz
The TCC2P card supports the E1 BITS OUT signal as defined in ITU-T G.703 Section 9, an d the BITS
OUT 2.048 MHz signal as defined in ITU-T G.703 Section 13. All of the BITS OUT signals meet the
output signal criteria (including jitter and wander) as defined in ITU-T G.813 Sections 5 and 6, ITU- T
G.811 Section 5, and ITU-T G.812, Section 6.
When SDH timing is selected, SDH Sync Status Messaging (SSM) is transmitted on the output ports and
received on the input ports. SSM can be enabled or disabled.
The following framing options are allowed when E1 2.048 MHz timing is selected:
• Frame Alignment Signal (FAS)
• Frame Alignment Signal plus Channel Associated Signal (FAS + CAS)
• Frame Alignment Signal plus Cyclic Redundancy Check (FAS + CRC)
• Frame Alignment Signal plus Channel Associated Signal plus Cyclic Redundancy Check (FAS +
CAS + CRC)