Chapter 3 Processor/Memory Subsystem

3.3.1 RAMBUS ATTRIBUTES

To ensure signal quality during high-speed memory transfers, the Rambus interface design departs from previous memory interface designs in several key aspects (Figure 3-4). Rambus uses a daisy- chained signal distribution system that requires that all memory sockets be populated with either a RIMM or a continuity module (CRIMM) in order to maintain constant load impedance. Rambus Signaling Levels (RSL) uses a 1.4-volt reference with a 0.8-volt swing between logic 0 at 1.8 V and logic 1 at 1.0 V.

On these systems RIMMs (or CRIMMs) must be installed in pairs (one module for each channel). A maximum of two gigabytes of memory may be installed using 512-MB RIMMs. These systems ship with PC800 (400-MHz) RIMMs but will also accept PC700 or PC600 RIMMs. A mix of ECC and non-ECC RIMMs may be installed, although all RIMMs must be ECC to realize ECC benefits.

 

 

 

 

 

 

RIMM or CRIMM (Shown)

 

 

 

RIMM

 

 

 

 

 

 

 

 

 

RIMM

MCH

Channel 1

 

 

 

 

 

Channel 2

 

 

Bus Termination

 

 

 

 

 

 

 

 

 

RIMM Sockets

 

 

 

 

 

 

 

 

 

 

 

Rambus Signal Attributes (Each Channel)

 

No. of

 

Input/

Signal

 

 

Signal Name

Lines

 

Output [1]

Level

Impedance

Function

ROW 2..0

3

 

O

RSL

28 ohms

Row address

COL 4..0

5

 

O

RSL

28 ohms

Column address

DQA 8..0

9

 

I/O

RSL

28 ohms

Data byte A (w/parity or ECC bit)

DQB 8..0

9

 

I/O

RSL

28 ohms

Data byte B (w/parity or ECC bit)

CFM, CFMN

2

 

O

RSL [2]

28 ohms

400-MHz Clock-from-master for writes

CTM, CTMN

2

 

I

RSL [2]

28 ohms

400-MHz Clock-to-master for reads

Vref

1

 

--

1.4 V

--

Reference voltage for RSL signals

SIO

1

 

I/O

CMOS

--

Serial I/F for initialization & pwr cntrl.

SCK

1

 

O

CMOS

56 ohms

SIO clock; 1 MHz for configuration,100

 

 

 

 

 

 

MHz for power management.

CMD

1

 

I/O

CMOS

56 ohms

Serial I/F config. & power control

Vdd

 

 

--

2.5 V

--

Power for Rambus circuitry

NOTES:

[1]Relative to the memory controller.

[2]Differential pair with Ep-p swing of 400 to 600 mV.

Figure 3–4.Rambus Channel Signal Distribution and Key Attributes

3-6Compaq Deskpro EXS and Workstation 300 Personal Computers

Featuring the Intel Pentium 4 Processor

First Edition - December 2000

Page 50
Image 50
Compaq 850 manual Rambus Attributes, Rambus Signal Attributes Each Channel, Signal Name