Compaq 850 manual Rambus Channel Transactions

Technical Reference Guide

3.3.2 RAMBUS CHANNEL TRANSACTIONS

Transactions on the Rambus Channel involve packets of control (row or column) bits and packets of data bits. Each packet consists of eight segments, with even segments transferred on falling clock edges and odd segments transferred on rising clock edges. A typical operation consists of the memory controller sending out a 24-bit row packet followed by a 40-bit column packet and then the 144-bit (128-bit for non-ECC) data packet being either written to or read from RDRAM (Figure 3-5).

Tn [1] Trc Tcd

Clock

ROW 2..0	0	1	2	3	4	5	6	7
COL 4..0								0	1	2	3	4	5	6	7
								Vref = 1.4			Logic 0 = 1.8 V
DQA 8..0															0	1	2	3	4	5	6	7
DQB 8..0											Logic 1 = 1.0 V
NOTE:			Row Packet							Column Packet							Data Packet

[1]Tn = 1.25 ns @ 400 MHz (PC800)

=1.42 ns @ 350 MHz (PC700)

=1.66 ns @ 300 MHz (PC600)

Figure 3–5.Rambus Transactions (Single Channel)

The clock signal is driven by the source device (i.e., by the memory controller during writes, by the RDRAM device during reads). The row (ROW) and column (COL) signal lines are driven only by the memory controller and assume the functions provided by the RAS/CAS signals of traditional memory buses. The ROW and COL signals are also used for power management and defining the type (read/write) of transaction. The data lines (DQAx/DQBx) are bi-directional, being driven by the controller during writes and by the RDRAM during reads. There is a specified delay period between related Row and Column packets (Trc, typically 7 clock cycles) and related column and data packets (Tcd, typically 8 to 12 clock cycles).

Note that while Figure 3-5 illustrates a single Rambus transaction, actual operation can involve pipelined transactions where back-to-back column packets are sent followed by back-to-back data packets. A row packet may be omitted if the row to be accessed is already open. Another important characteristic is that the ROW, COL, and DQA/DQB signal lines act as independent buses and simultaneous transfers of row, column, and data information can take place.

Compaq Deskpro EXS and Workstation 300 Personal Computers 3-7

Featuring the Intel Pentium 4 Processor

First Edition - December 2000