Cypress manual CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25, Features

CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Features

•Supports 133 MHz bus operations

•512K x 36/1M x 18 common IO

•2.5V core power supply (VDD)

•2.5V IO supply (VDDQ)

•Fast clock-to-output times, 6.5 ns (133 MHz version)

•Provides high-performance 2-1-1-1 access rate

•User selectable burst counter supporting Intel→ Pentium→ interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self timed write

•Asynchronous output enable

•CY7C1381DV25/CY7C1383DV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1381FV25/CY7C1383FV25 available in Pb-free and non Pb-free 119-ball BGA package

•IEEE 1149.1 JTAG-Compatible Boundary Scan

•ZZ sleep mode option

Selection Guide

Functional Description [1]

The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/ CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3 [2]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWx, and BWE), and global

write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/ CY7C1383FV25 allows interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.

Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV).

The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/ CY7C1383FV25 operates from a +2.5V core power supply while all outputs also operate with a +2.5 supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.

	133 MHz	100 MHz	Unit
Maximum Access Time	6.5	8.5	ns
Maximum Operating Current	210	175	mA
Maximum CMOS Standby Current	70	70	mA

Notes

1.For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2.CE3, CE2 are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 chip enable.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05547 Rev. *E		Revised Feburary 14, 2007

[+] Feedback