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Cypress CY7C1383DV25 manual Pin Configurations continued 119-Ball BGA Pinout, CY7C1381FV25 512K x

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

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CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Pin Configurations (continued)

119-Ball BGA Pinout

CY7C1381FV25 (512K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

VDDQ

ADSP

B

NC/288M

A

NC/576M

ADSC

C

NC/144M

A

VDD

A

NC/1G

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

VSS

1

VSS

DQB

CE

F

VDDQ

DQC

VSS

DQB

VDDQ

OE

G

DQC

C

B

DQB

BW

ADV

BW

H

DQC

VSS

DQB

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD

VSS

CLK

VSS

DQA

L

DQD

D

NC

A

DQA

BW

M

VDDQ

DQD

VSS

DQA

VDDQ

BWE

N

DQD

VSS

A1

VSS

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC/72M

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1383FV25 (1M x 18)

1

2

3

4

5

6

7

A

VDDQ

A

VDDQ

ADSP

B

NC/288M

A

NC/576M

ADSC

C

NC/144M

A

VDD

A

NC/1G

D

DQB

NC

VSS

NC

VSS

DQPA

NC

E

NC

DQB

VSS

1

VSS

NC

DQA

CE

F

VDDQ

NC

VSS

DQA

VDDQ

OE

G

NC

DQB

B

NC

DQA

BW

ADV

H

DQB

NC

VSS

DQA

NC

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB

VSS

CLK

VSS

NC

DQA

L

DQB

NC

A

DQA

NC

BW

M

VDDQ

DQB

VSS

NC

VDDQ

BWE

N

DQB

NC

VSS

A1

VSS

DQA

NC

P

NC

DQPB

VSS

A0

VSS

NC

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC/72M

A

NC/36M

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05547 Rev. *E

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Cypress CY7C1383DV25 manual Pin Configurations continued 119-Ball BGA Pinout, CY7C1381FV25 512K x, CY7C1383FV25 1M x

Contents

Features CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Selection Guide Functional DescriptionLogic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K x Logic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M xCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Pin Configurations 100-pin TQFP Pinout 3 Chip Enable CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25 512K xPin Configurations continued 119-Ball BGA Pinout CY7C1381FV25 512K xCY7C1383FV25 1M x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Pin Configurations continued 165-Ball FBGA Pinout3 Chip Enable CY7C1381DV25 512K xCY7C1383DV25 1Mx CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Pin Definitions CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Name DescriptionPin Definitions continued Functional OverviewCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25ZZ Mode Electrical Characteristics CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Interleaved Burst Address Table MODE = Floating or VDD AddressCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Truth Table 4, 5, 6, 7CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Truth Table for Read/Write 4Truth Table for Read/Write TAP Controller State Diagram TAP Controller Block DiagramIEEE 1149.1 Serial Boundary Scan JTAG Disabling the JTAG FeatureCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 TAP Instruction SetTAP AC Switching Characteristics TAP TimingCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Reserved2.5V TAP AC Test Conditions 2.5V TAP AC Output Load EquivalentIdentification Register Definitions Scan Register SizesIdentification Codes 119-Ball BGA Boundary Scan Order 13CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV2515. Bit #89 is preset HIGH 165-Ball BGA Boundary Scan Order 13CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Electrical Characteristics Maximum RatingsOperating Range Ambient TemperatureCapacitance Thermal ResistanceAC Test Loads and Waveforms CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Switching Characteristics CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Timing Diagrams CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Read Cycle Timing + FeedbackTiming Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25+ Feedback Data in DTiming Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Read/Write Cycle Timing 25, 27 Page 22 ofTiming Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25ZZ Mode Timing 29 Page 23 ofOrdering Information CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Package Diagrams CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Figure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm + FeedbackPackage Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Figure 2. 119-Ball BGA 14 x 22 x 2.4 mm + FeedbackPackage Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Figure 3. 165-Ball FBGA 13 x 15 x 1.4 mm 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165DDocument History Page Issue DateCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Flow-Through SRAM Document Number