Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1381FV25, CY7C1383DV25 Timing Diagrams continued, + Feedback, Data in D, Data Out Q

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25

Timing Diagrams (continued)

Write Cycle Timing [25, 26]

	tCYC
CLK	t CL
t CH	t CL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for ﬁrst cycle when

ADSP initiates burst

BWE,

BW X

t t

WES WEH

ADSC extends burst

tADS tADH

tWES tWEH

tCES tCEH

ADV

Data in (D)

High-Z

Data Out (Q)

tOEHZ

t DS t DH

D(A1)

tADVS tADVH

ADV suspends burst

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST READ

Single WRITE

BURST WRITE
DON’T CARE	UNDEFINED

Extended BURST WRITE

Note

26. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BWX LOW.

Document #: 38-05547 Rev. *E

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[+] Feedback

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Cypress manual Timing Diagrams continued, CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25, + Feedback, Data in D

Contents

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 FeaturesSelection Guide Functional DescriptionLogic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M x Logic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K xCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations 100-pin TQFP Pinout 3 Chip EnableCY7C1381DV25 512K xCY7C1381FV25 512K x Pin Configurations continued 119-Ball BGA PinoutCY7C1383FV25 1M x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25 512K x Pin Configurations continued 165-Ball FBGA Pinout3 Chip EnableCY7C1383DV25 1Mx CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin DefinitionsName DescriptionFunctional Overview Pin Definitions continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table MODE = Floating or VDD AddressTruth Table 4, 5, 6, 7 CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Truth Table for Read/Write 4 CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Truth Table for Read/Write TAP Controller Block Diagram TAP Controller State DiagramIEEE 1149.1 Serial Boundary Scan JTAG Disabling the JTAG FeatureTAP Instruction Set CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25TAP Timing TAP AC Switching CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Reserved2.5V TAP AC Output Load Equivalent 2.5V TAP AC Test ConditionsIdentification Register Definitions Scan Register Sizes119-Ball BGA Boundary Scan Order 13 Identification CodesCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25165-Ball BGA Boundary Scan Order 13 15. Bit #89 is preset HIGHCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Maximum Ratings Electrical CharacteristicsOperating Range Ambient TemperatureThermal Resistance CapacitanceAC Test Loads and Waveforms CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Switching CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing DiagramsRead Cycle Timing + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continued+ Feedback Data in DCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continuedRead/Write Cycle Timing 25, 27 Page 22 ofCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continuedZZ Mode Timing 29 Page 23 ofCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Ordering InformationCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package DiagramsFigure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package Diagrams continuedFigure 2. 119-Ball BGA 14 x 22 x 2.4 mm + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package Diagrams continuedFigure 3. 165-Ball FBGA 13 x 15 x 1.4 mm 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165DIssue Date Document History PageCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Flow-Through SRAM Document Number