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Cypress manual CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25, Timing Diagrams continued

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25

Timing Diagrams (continued)

Read/Write Cycle Timing [25, 27, 28]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

ADSC

tAS tAH

ADDRESS

tWES t WEH

BWE, BW X

tCES tCEH

A5A6

CE
ADV
OE
Data In (D)	High-Z	t
		OEHZ
Data Out (Q)	Q(A1)	Q(A2)
	Back-to-Back READs

tDS	tDH
	tOELZ

D(A3)
tCDV
Q(A4)	Q(A4+1)	Q(A4+2)	Q(A4+3)
Single WRITE	BURST READ
DON’T CARE	UNDEFINED

D(A5) D(A6)

Back-to-Back

WRITEs

Notes

27.The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.

28.GW is HIGH.

Document #: 38-05547 Rev. *E

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Contents

Selection Guide FeaturesCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Functional DescriptionCY7C1381DV25, CY7C1381FV25 Logic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K xLogic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M x CY7C1383DV25, CY7C1383FV25CY7C1381DV25 Pin Configurations 100-pin TQFP Pinout 3 Chip EnableCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 512K xCY7C1383FV25 1M x Pin Configurations continued 119-Ball BGA PinoutCY7C1381FV25 512K x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1383DV25 1Mx Pin Configurations continued 165-Ball FBGA Pinout3 Chip EnableCY7C1381DV25 512K x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Name Pin DefinitionsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 DescriptionCY7C1381DV25, CY7C1381FV25 Pin Definitions continuedFunctional Overview CY7C1383DV25, CY7C1383FV25Interleaved Burst Address Table MODE = Floating or VDD ZZ Mode Electrical CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 AddressCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Truth Table 4, 5, 6, 7CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Truth Table for Read/Write 4Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan JTAG TAP Controller State DiagramTAP Controller Block Diagram Disabling the JTAG FeatureCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 TAP Instruction SetCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 TAP AC Switching CharacteristicsTAP Timing ReservedIdentification Register Definitions 2.5V TAP AC Test Conditions2.5V TAP AC Output Load Equivalent Scan Register SizesCY7C1381DV25, CY7C1381FV25 Identification Codes119-Ball BGA Boundary Scan Order 13 CY7C1383DV25, CY7C1383FV2515. Bit #89 is preset HIGH 165-Ball BGA Boundary Scan Order 13CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Operating Range Electrical CharacteristicsMaximum Ratings Ambient TemperatureAC Test Loads and Waveforms CapacitanceThermal Resistance CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Switching Characteristics CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Read Cycle Timing Timing DiagramsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 + Feedback+ Feedback Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Data in DRead/Write Cycle Timing 25, 27 Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Page 22 ofZZ Mode Timing 29 Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Page 23 ofOrdering Information CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Figure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 + FeedbackFigure 2. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 + FeedbackFigure 3. 165-Ball FBGA 13 x 15 x 1.4 mm Package Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165DCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document History PageIssue Date Flow-Through SRAM Document Number