CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Pin Definitions
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| A0, A1, A | Input- | Address inputs used to select one of the address locations. Sampled at the rising edge | ||||||||||||||||||||||||
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| Synchronous | of the CLK if ADSP or | ADSC | is active LOW, and CE | 1 | , CE | 2 | , and CE [2] are sampled active. | ||||||||
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| A[1:0] feed the |
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| 3 | |||||||||||
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| A, |
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| B | Input- | Byte write select inputs, active LOW. Qualified with |
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| to conduct byte writes to the | |||||||||||||
| BW | BW | BWE | ||||||||||||||||||||||||
| BWC, BWD | Synchronous | SRAM. Sampled on the rising edge of CLK. |
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| Input- | Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a | ||||||||||||||||
| GW | ||||||||||||||||||||||||||
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| Synchronous | global write is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE). | ||||||||||||||
| CLK | Input- | Clock input. Used to capture all synchronous inputs to the device. Also used to increment | ||||||||||||||||||||||||
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| Clock | the burst counter when ADV is asserted LOW, during a burst operation. | ||||||||||||||
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| 1 |
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| Input- | Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction | |||||||||||||||||||
| CE | ||||||||||||||||||||||||||
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| Synchronous | with CE2 and |
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| 3 [2] to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 | |||||||||||
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| CE | |||||||||||||||
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| is sampled only when a new external address is loaded. |
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| CE2 | Input- | Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction | ||||||||||||||||||||||||
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| Synchronous | with CE |
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| [2] to select or deselect the device. CE |
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| 1 | CE | 3 |
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| 2 |
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| external address is loaded. |
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| 3 [2] | Input- | Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction | |||||||||||||||||||||||
| CE | ||||||||||||||||||||||||||
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| Synchronous | with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external | ||||||||||||||
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| address is loaded. |
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| Input- | Output enable, asynchronous input, active LOW. Controls the direction of the IO pins. | ||||||||||||||||||
| OE | ||||||||||||||||||||||||||
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| Asynchronous | When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are | ||||||||||||||
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| and act as input data pins. OE is masked during the first clock of a read cycle when emerging | ||||||||||||||
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| from a deselected state. |
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| Input- | Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically | ||||||||||||||||
| ADV | ||||||||||||||||||||||||||
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| Synchronous | increments the address in a burst cycle. |
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| Input- | Address strobe from processor, sampled on the rising edge of CLK, active LOW. When | |||||||||||||||
| ADSP | ||||||||||||||||||||||||||
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| Synchronous | asserted LOW, addresses presented to the device are captured in the address registers. | ||||||||||||||
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| A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only | ||||||||||||||
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| ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. | ||||||||||||||
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| Input- | Address strobe from controller, sampled on the rising edge of CLK, active LOW. When | |||||||||||||||
| ADSC | ||||||||||||||||||||||||||
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| Synchronous | asserted LOW, addresses presented to the device are captured in the address registers. | ||||||||||||||
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| A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only | ||||||||||||||
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| ADSP is recognized. |
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| Input- | Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must | ||||||||||||||||||
| BWE | ||||||||||||||||||||||||||
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| Synchronous | be asserted LOW to conduct a byte write. |
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| ZZ | Input- | ZZ sleep input. This active HIGH input places the device in a | ||||||||||||||||||||||||
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| Asynchronous | condition with data integrity preserved. For normal operation, this pin has to be LOW or left | ||||||||||||||
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| floating. ZZ pin has an internal pull down. |
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| DQs | IO- | Bidirectional data IO lines. As inputs, they feed into an | ||||||||||||||||||||||||
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| Synchronous | by the rising edge of CLK. As outputs, they deliver the data contained in the memory location | ||||||||||||||
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| specified by the addresses presented during the previous clock rise of the read cycle. The | ||||||||||||||
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| direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as | ||||||||||||||
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| outputs. When HIGH, DQs and DQPX are placed in a | ||||||||||||||
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| automatically | ||||||||||||||
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| when emerging from a deselected state, and when the device is deselected, regardless of | ||||||||||||||
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| the state of OE. |
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| DQPX | IO- | Bidirectional data parity IO lines. Functionally, these signals are identical to DQs. During | ||||||||||||||||||||||||
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| Synchronous | write sequences, DQPX is controlled by BWX correspondingly. | ||||||||||||||
Document #: |
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| Page 6 of 28 |
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