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Cypress CY7C1383FV25 Pin Configurations 100-pin TQFP Pinout 3 Chip Enable, CY7C1381DV25, 512K x

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

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Pin Configurations

CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Pin Configurations

100-pin TQFP Pinout (3 Chip Enable)

DQPC

DQC DQC

VDDQ

VSSQ

DQC

DQC

DQC

DQC

VSSQ

VDDQ

DQC

DQC

NC

VDD

NC

VSS

DQD

DQD

VDDQ

VSSQ

DQD

DQD

DQD

DQD

VSSQ

VDDQ

DQD DQD DQPD

	A A CE						CE		BWD BWC BWB BWA CE V V CLK GW																	BWE OE			ADSC			ADSP	ADV A A
1							2									3 DD SS
																3 DD SS


100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1																													80
2																													79
3																													78
4																													77
5																													76
6																													75
7																													74
8																													73
9																													72
10																													71
11																													70
12																													69
13																													68
14																													67
15											CY7C1381DV25																		66
16											CY7C1381DV25																		65
17													(512K x 36)																64
18																													63
19																													62
20																													61
21																													60
22																													59
23																													58
24																													57
25																													56
26																													55
27																													54
28																													53
29																													52
30																													51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DQPB	NC
DQB	NC
DQB	NC
VDDQ	V
VSSQ	DDQ
VSSQ	V
DQB	SSQ
DQB	NC
DQB	NC
DQB	DQ
DQB	B
DQB	DQ
VSSQ	B
VSSQ	V
VDDQ	SSQ
VDDQ	V
DQB	DDQ
DQB	DQ
DQB	B
DQB	DQ
VSS	B
VSS	NC
NC	VDD
VDD	NC
ZZ	VSS
DQA	DQ
DQA	B
DQA	DQ
VDDQ	B
VDDQ	V
VSSQ	DDQ
VSSQ	V
DQA	SSQ
DQA	DQ
DQA	B
DQA	DQ
DQA	B
DQA	DQP
DQA	B
DQA	NC
VSSQ	V
VDDQ	SSQ
VDDQ	V
DQA	DDQ
DQA	NC
DQA	NC
DQPA	NC

1 2															3				DD SS								BWE				ADSC		ADSP
	A A												BWB		BWA				DD SS																	ADV A A
	A A				CE CE				NC NC				BWB		BWA		CE		V V CLK						GW				OE							ADV A A


100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1																															80
2																															79
3																															78
4																															77
5																															76
6																															75
7																															74
8																															73
9																															72
10																															71
11																															70
12																															69
13																															68
14													CY7C1383DV25																		67
15													CY7C1383DV25																		66
16														(1 Mbit x 18)																	65
17														(1 Mbit x 18)																	64
17																															64
18																															63
19																															62
20																															61
21																															60
22																															59
23																															58
24																															57
25																															56
26																															55
27																															54
28																															53
29																															52
30																															51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A

NC

NC

VDDQ

VSSQ NC DQPA DQA DQA

VSSQ VDDQ

DQA DQA VSS NC VDD ZZ DQA DQA

VDDQ VSSQ

DQA DQA NC NC

VSSQ

VDDQ NC NC NC

MODE A A A A A	A	NC NC V V A A A A A A A A A
1	0	SS DD

1 0	SS DD
MODE A A A A A A	NC NC V V	A A A A A A A A A

Document #: 38-05547 Rev. *E

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Cypress CY7C1383FV25 Pin Configurations 100-pin TQFP Pinout 3 Chip Enable, CY7C1381DV25, 512K x, CY7C1383DV25, Mbit x

Contents

Functional Description FeaturesCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Selection GuideCY7C1383DV25, CY7C1383FV25 Logic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K xLogic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M x CY7C1381DV25, CY7C1381FV25512K x Pin Configurations 100-pin TQFP Pinout 3 Chip EnableCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 CY7C1381DV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations continued 119-Ball BGA PinoutCY7C1381FV25 512K CY7C1383FV25 1M xCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations continued 165-Ball FBGA Pinout3 Chip EnableCY7C1381DV25 512K x CY7C1383DV25 1MxDescription Pin DefinitionsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 NameCY7C1383DV25, CY7C1383FV25 Pin Definitions continuedFunctional Overview CY7C1381DV25, CY7C1381FV25Address ZZ Mode Electrical CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Interleaved Burst Address Table MODE = Floating or VDDTruth Table 4, 5, 6, 7 CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Truth Table for Read/Write 4 CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Truth Table for Read/Write Disabling the JTAG Feature TAP Controller State DiagramTAP Controller Block Diagram IEEE 1149.1 Serial Boundary Scan JTAGTAP Instruction Set CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Reserved TAP AC Switching CharacteristicsTAP Timing CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Scan Register Sizes 2.5V TAP AC Test Conditions2.5V TAP AC Output Load Equivalent Identification Register DefinitionsCY7C1383DV25, CY7C1383FV25 Identification Codes119-Ball BGA Boundary Scan Order 13 CY7C1381DV25, CY7C1381FV25165-Ball BGA Boundary Scan Order 13 15. Bit #89 is preset HIGHCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Electrical CharacteristicsMaximum Ratings Operating RangeCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 CapacitanceThermal Resistance AC Test Loads and WaveformsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Switching Characteristics+ Feedback Timing DiagramsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Read Cycle TimingData in D Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 + FeedbackPage 22 of Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Read/Write Cycle Timing 25, 27Page 23 of Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 ZZ Mode Timing 29CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Ordering Information+ Feedback Package DiagramsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Figure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm+ Feedback Package Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Figure 2. 119-Ball BGA 14 x 22 x 2.4 mm165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D Package Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Figure 3. 165-Ball FBGA 13 x 15 x 1.4 mmFlow-Through SRAM Document Number Document History PageIssue Date CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25