Cypress CY7C1383FV25, CY7C1383DV25, CY7C1381FV25, CY7C1381DV25 manual Switching Characteristics

CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Switching Characteristics

Over the Operating Range [19, 20]

Parameter

Description

133 MHz

100 MHz

Unit

Min.

Max.

Min.

Max.

t

POWER

V (Typical) to the first Access [21]

1

1

ms

DD

Clock

tCYC

Clock Cycle Time

7.5

10

ns

tCH

Clock HIGH

2.1

2.5

ns

tCL

Clock LOW

2.1

2.5

ns

Output Times

tCDV

Data Output Valid After CLK Rise

6.5

8.5

ns

tDOH

Data Output Hold After CLK Rise

2.0

2.0

ns

tCLZ

Clock to Low-Z [22, 23, 24]

2.0

2.0

ns

tCHZ

Clock to High-Z [22, 23, 24]

0

4.0

0

5.0

ns

tOEV

LOW to Output Valid

3.2

3.8

ns

OE

tOELZ

LOW to Output Low-Z [22, 23, 24]

0

0

ns

OE

tOEHZ

HIGH to Output High-Z [22, 23, 24]

4.0

5.0

ns

OE

Setup Times

tAS

Address Setup Before CLK Rise

1.5

1.5

ns

tADS

Setup Before CLK Rise

1.5

1.5

ns

ADSP,

ADSC

tADVS

Setup Before CLK Rise

1.5

1.5

ns

ADV

tWES

[A:D] Setup Before CLK Rise

1.5

1.5

ns

GW,

BWE,

BW

tDS

Data Input Setup Before CLK Rise

1.5

1.5

ns

tCES

Chip Enable Setup

1.5

1.5

ns

Hold Times

tAH

Address Hold After CLK Rise

0.5

0.5

ns

tADH

Hold After CLK Rise

0.5

0.5

ns

ADSP,

ADSC

tWEH

[A:D] Hold After CLK Rise

0.5

0.5

ns

GW,

BWE,

BW

tADVH

Hold After CLK Rise

0.5

0.5

ns

ADV

tDH

Data Input Hold After CLK Rise

0.5

0.5

ns

tCEH

Chip Enable Hold After CLK Rise

0.5

0.5

ns

Notes

19.Timing reference level is 1.25V.

20.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

21.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated.

22.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

23.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

24.This parameter is sampled and not 100% tested.

Document #: 38-05547 Rev. *E Page 19 of 28

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