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Cypress CY7C1381FV25, CY7C1383DV25 Pin Configurations continued 165-Ball FBGA Pinout3 Chip Enable

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

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Pin Configurations (continued)

CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Pin Configurations (continued)

165-Ball FBGA Pinout(3 Chip Enable)

CY7C1381DV25 (512K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/288M

1

C

B

3

A

NC

A

CE

BW

BW

CE

BWE

ADSC

ADV

B

NC/144M

A

CE2

D

A

CLK

A

NC/576M

BW

BW

GW

OE

ADSP

C

DQPC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC/1G

DQPB

D

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

E

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

F

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

G

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

K

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

L

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

M

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

N

DQPD

NC

VDDQ

VSS

NC

A

NC

VSS

VDDQ

NC

DQPA

P

NC

NC/72M

A

A

TDI

A1

TDO

A

A

A

A

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

CY7C1383DV25 (1Mx 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/288M

A

1

B

NC

3

A

A

CE

BW

CE

BWE

ADSC

ADV

B

NC/144M

A

CE2

NC

A

CLK

A

NC/576M

BW

GW

OE

ADSP

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC/1G

DQPA

D

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

E

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

F

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

G

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

H

VSS

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

K

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

L

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

M

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

N

DQPB

NC

VDDQ

VSS

NC

A

NC

VSS

VDDQ

NC

NC

P

NC

NC/72M

A

A

TDI

A1

TDO

A

A

A

A

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

Document #: 38-05547 Rev. *E

Page 5 of 28

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Cypress CY7C1381FV25 Pin Configurations continued 165-Ball FBGA Pinout3 Chip Enable, CY7C1381DV25 512K x, CY7C1383DV25 1Mx

Contents

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 FeaturesSelection Guide Functional DescriptionLogic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M x Logic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K xCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations 100-pin TQFP Pinout 3 Chip EnableCY7C1381DV25 512K xCY7C1381FV25 512K x Pin Configurations continued 119-Ball BGA PinoutCY7C1383FV25 1M x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25 512K x Pin Configurations continued 165-Ball FBGA Pinout3 Chip EnableCY7C1383DV25 1Mx CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin DefinitionsName DescriptionFunctional Overview Pin Definitions continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table MODE = Floating or VDD AddressTruth Table 4, 5, 6, 7 CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Truth Table for Read/Write Truth Table for Read/Write 4CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 TAP Controller Block Diagram TAP Controller State DiagramIEEE 1149.1 Serial Boundary Scan JTAG Disabling the JTAG FeatureTAP Instruction Set CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25TAP Timing TAP AC Switching CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Reserved2.5V TAP AC Output Load Equivalent 2.5V TAP AC Test ConditionsIdentification Register Definitions Scan Register Sizes119-Ball BGA Boundary Scan Order 13 Identification CodesCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 165-Ball BGA Boundary Scan Order 1315. Bit #89 is preset HIGH Maximum Ratings Electrical CharacteristicsOperating Range Ambient TemperatureThermal Resistance CapacitanceAC Test Loads and Waveforms CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Switching CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing DiagramsRead Cycle Timing + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continued+ Feedback Data in DCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continuedRead/Write Cycle Timing 25, 27 Page 22 ofCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continuedZZ Mode Timing 29 Page 23 ofCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Ordering InformationCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package DiagramsFigure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package Diagrams continuedFigure 2. 119-Ball BGA 14 x 22 x 2.4 mm + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package Diagrams continuedFigure 3. 165-Ball FBGA 13 x 15 x 1.4 mm 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165DIssue Date Document History PageCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Flow-Through SRAM Document Number