Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress Package Diagrams, CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25, + Feedback

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

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CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Package Diagrams

Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

100

1.40±0.05

22.00±0.20

20.00±0.10

0.30±0.08

0.65	12° ±1°
TYP.	(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN. 0.20 MAX.

0.25

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.NOTE:

0.15 MAX.

0.10

GAUGE PLANE

0° -7°

0.60±0.15

1.00 REF.

R 0.08 MIN. 0.20 MAX.

0.20 MIN.

DETAIL A

1.JEDEC STD REF MS-026

2.BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3.DIMENSIONS IN MILLIMETERS

51-85050-*B

Document #: 38-05547 Rev. *E

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Cypress manual Package Diagrams, CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25, + Feedback

Contents

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 FeaturesSelection Guide Functional DescriptionLogic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M x Logic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K xCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations 100-pin TQFP Pinout 3 Chip EnableCY7C1381DV25 512K xCY7C1381FV25 512K x Pin Configurations continued 119-Ball BGA PinoutCY7C1383FV25 1M x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25 512K x Pin Configurations continued 165-Ball FBGA Pinout3 Chip EnableCY7C1383DV25 1Mx CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin DefinitionsName DescriptionFunctional Overview Pin Definitions continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table MODE = Floating or VDD AddressTruth Table 4, 5, 6, 7 CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Truth Table for Read/Write 4Truth Table for Read/Write TAP Controller Block Diagram TAP Controller State DiagramIEEE 1149.1 Serial Boundary Scan JTAG Disabling the JTAG FeatureTAP Instruction Set CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25TAP Timing TAP AC Switching CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Reserved2.5V TAP AC Output Load Equivalent 2.5V TAP AC Test ConditionsIdentification Register Definitions Scan Register Sizes119-Ball BGA Boundary Scan Order 13 Identification CodesCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV2515. Bit #89 is preset HIGH 165-Ball BGA Boundary Scan Order 13CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Maximum Ratings Electrical CharacteristicsOperating Range Ambient TemperatureThermal Resistance CapacitanceAC Test Loads and Waveforms CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Switching CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing DiagramsRead Cycle Timing + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continued+ Feedback Data in DCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continuedRead/Write Cycle Timing 25, 27 Page 22 ofCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Timing Diagrams continuedZZ Mode Timing 29 Page 23 ofCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Ordering InformationCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package DiagramsFigure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package Diagrams continuedFigure 2. 119-Ball BGA 14 x 22 x 2.4 mm + FeedbackCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Package Diagrams continuedFigure 3. 165-Ball FBGA 13 x 15 x 1.4 mm 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165DIssue Date Document History PageCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Flow-Through SRAM Document Number