Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress Timing Diagrams, CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25, + Feedback

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

1 28

Download 28 pages 41.6 Kb

Page 20

Image 20

CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Timing Diagrams

Read Cycle Timing [25]

tCYC

CLK

t CH

tADS tADH

t CL

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS

GW, BWE,BW

A1	A2
t WES	t WEH
tCES t CEH	Deselect Cycle
tCES t CEH
	t ADVS t ADVH

ADV
OE
		tOEV
		tOEHZ
		tCLZ
Data Out (Q)	High-Z	Q(A1)

tCDV

Single READ

ADV suspends burst

t	tCDV
	OELZ
	tCHZ
	tDOH

Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)	Q(A2)	Q(A2 + 1)	Q(A2 + 2)
				Burst wraps around
		BURST		to its initial state
		BURST
		READ
	DON’T CARE	UNDEFINED

Note

25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05547 Rev. *E

Page 20 of 28

[+] Feedback

Page 20

Image 20

Cypress manual Timing Diagrams, CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25, Read Cycle Timing, + Feedback

Contents

Features CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Selection Guide Functional DescriptionLogic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K x Logic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M xCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Pin Configurations 100-pin TQFP Pinout 3 Chip Enable CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25 512K xPin Configurations continued 119-Ball BGA Pinout CY7C1381FV25 512K xCY7C1383FV25 1M x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Pin Configurations continued 165-Ball FBGA Pinout3 Chip Enable CY7C1381DV25 512K xCY7C1383DV25 1Mx CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Pin Definitions CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Name DescriptionPin Definitions continued Functional OverviewCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25ZZ Mode Electrical Characteristics CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Interleaved Burst Address Table MODE = Floating or VDD AddressCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Truth Table 4, 5, 6, 7Truth Table for Read/Write Truth Table for Read/Write 4CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 TAP Controller State Diagram TAP Controller Block DiagramIEEE 1149.1 Serial Boundary Scan JTAG Disabling the JTAG FeatureCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 TAP Instruction SetTAP AC Switching Characteristics TAP TimingCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Reserved2.5V TAP AC Test Conditions 2.5V TAP AC Output Load EquivalentIdentification Register Definitions Scan Register SizesIdentification Codes 119-Ball BGA Boundary Scan Order 13CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 165-Ball BGA Boundary Scan Order 1315. Bit #89 is preset HIGH Electrical Characteristics Maximum RatingsOperating Range Ambient TemperatureCapacitance Thermal ResistanceAC Test Loads and Waveforms CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Switching Characteristics CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Timing Diagrams CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Read Cycle Timing + FeedbackTiming Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25+ Feedback Data in DTiming Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Read/Write Cycle Timing 25, 27 Page 22 ofTiming Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25ZZ Mode Timing 29 Page 23 ofOrdering Information CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Package Diagrams CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Figure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm + FeedbackPackage Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Figure 2. 119-Ball BGA 14 x 22 x 2.4 mm + FeedbackPackage Diagrams continued CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Figure 3. 165-Ball FBGA 13 x 15 x 1.4 mm 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165DDocument History Page Issue DateCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Flow-Through SRAM Document Number