Cypress CY7C1381DV25 manual 2.5V TAP AC Test Conditions, 2.5V TAP AC Output Load Equivalent

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25

2.5V TAP AC Test Conditions

Input pulse levels	VSS to 2.5V
Input rise and fall time	1 ns
Input timing reference levels	1.25V
Output reference levels	1.25V
Test load termination supply voltage	1.25V

2.5V TAP AC Output Load Equivalent

1.25V

50Ω

TDO

ZO= 50 Ω 20pF

TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted) [12]

Parameter	Description		Test Conditions		Min.	Max.	Unit
VOH1	Output HIGH Voltage	IOH = –1.0 mA, VDDQ = 2.5V			2.0		V
VOH2	Output HIGH Voltage	IOH = –100 µA, VDDQ = 2.5V			2.1		V
VOL1	Output LOW Voltage	IOL = 8.0 mA, VDDQ = 2.5V				0.4	V
VOL2	Output LOW Voltage	IOL = 100 µA		VDDQ = 2.5V		0.2	V
VIH	Input HIGH Voltage			VDDQ = 2.5V	1.7	VDD + 0.3	V
VIL	Input LOW Voltage			VDDQ = 2.5V	–0.3	0.7	V
IX	Input Load Current	GND < VIN < VDDQ			–5	5	µA

Identification Register Definitions

Instruction Field	CY7C1381DV25/	CY7C1383DV25/	Description
	CY7C1381FV25	CY7C1383FV25
	(512K x 36)	(1 Mbit x 18)
Revision Number (31:29)	000	000	Describes the version number
Device Depth (28:24)	01011	01011	Reserved for internal use.
Device Width (23:18) 119-BGA	101001	101001	Defines the memory type and architecture
Device Width (23:18) 165-FBGA	000001	000001	Defines the memory type and architecture
Cypress Device ID (17:12)	100101	010101	Defines the width and density
Cypress JEDEC ID Code (11:1)	00000110100	00000110100	Allows unique identification of SRAM vendor
ID Register Presence Indicator (0)	1	1	Indicates the presence of an ID register

Scan Register Sizes

Register Name	Bit Size (x36)	Bit Size (x18)
Instruction Bypass	3	3
Bypass	1	1
ID	32	32
Boundary Scan Order (119-ball BGA package)	85	85
Boundary Scan Order (165-ball FBGA package)	89	89

Note

12. All voltages referenced to VSS (GND).

Document #: 38-05547 Rev. *E Page 14 of 28

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