CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Truth Table [4, 5, 6, 7, 8]

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycle Description

CE1

CE2

CE3

ZZ

ADSP

 

ADSC

 

ADV

 

 

WRITE

 

OE

 

CLK

DQ

Used

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

H

X

 

X

 

L

 

X

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

L

 

X

 

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

X

 

H

 

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

L

 

X

 

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

X

X

 

X

 

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode, Power Down

None

 

X

X

 

X

 

H

 

X

 

X

 

X

 

 

X

 

X

 

X

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

L

 

X

 

X

 

 

X

 

L

 

L-H

Q

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

L

 

X

 

X

 

 

X

 

H

 

L-H

Tri-State

Write Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

X

 

 

L

 

X

 

L-H

D

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

X

 

 

H

 

L

 

L-H

Q

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

X

 

 

H

 

H

 

L-H

Tri-State

Read Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

L

 

 

H

 

L

 

L-H

Q

Read Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

Read Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

4.X = Don't Care, H = Logic HIGH, L = Logic LOW.

5.WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

6.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

7.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle.

8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05547 Rev. *E

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Cypress CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, CY7C1383FV25 manual Address Cycle Description, Used

CY7C1383DV25, CY7C1381FV25, CY7C1381DV25, CY7C1383FV25 specifications

Cypress Semiconductor's family of static random-access memory (SRAM) chips, including the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25, are designed for high-performance applications that require fast access times and low power consumption. These devices are often found in applications such as networking, telecommunications, and industrial control systems, where speed and reliability are paramount.

The CY7C1381FV25 and CY7C1381DV25 are single-port SRAMs, while the CY7C1383FV25 and CY7C1383DV25 are dual-port versions that allow for simultaneous read and write operations from two different controllers. This feature significantly enhances data throughput, making these devices ideal for high-bandwidth applications. The devices support asynchronous read and write operations, ensuring immediate data accessibility with minimal latency.

One of the key features of these SRAM chips is their fast access times, with read and write cycles as short as 10 nanoseconds. This speed makes them suitable for cache memory applications, where performance is critical. Furthermore, the devices are built on Cypress's advanced process technology, which enables them to achieve high density and low power consumption, ideal for battery-operated devices and systems where energy efficiency is crucial.

The power consumption characteristics also highlight their effectiveness in various applications. The active power consumption can be as low as 80mA, depending on the operation conditions, and the devices offer low standby power, further enhancing their suitability for low-power applications. Additionally, these chips incorporate power-saving features like sleep mode, allowing designers to minimize energy consumption in idle states.

In terms of reliability, Cypress employs rigorous quality control measures, ensuring that the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 meet stringent industry standards. They also feature an extended temperature range, which is vital for industrial applications that may experience harsh environmental conditions.

Overall, the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 SRAM chips are versatile, high-performance memory solutions. Their combination of fast access times, low power consumption, and reliability makes them an excellent choice for engineers and developers looking to implement high-speed memory in a variety of applications. Whether for a communication device or a sophisticated industrial control system, these Cypress SRAMs stand out in the market for their performance and efficiency.