Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress manual CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25, Timing Diagrams continued

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25

Timing Diagrams (continued)

ZZMode Timing [29, 30]

CLK

t ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes

29.Device must be deselected when entering ZZ sleep mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

30.DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05547 Rev. *E

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Contents

Functional Description FeaturesCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Selection GuideCY7C1383DV25, CY7C1383FV25 Logic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K xLogic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M x CY7C1381DV25, CY7C1381FV25512K x Pin Configurations 100-pin TQFP Pinout 3 Chip EnableCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 CY7C1381DV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations continued 119-Ball BGA PinoutCY7C1381FV25 512K x CY7C1383FV25 1M xCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Pin Configurations continued 165-Ball FBGA Pinout3 Chip EnableCY7C1381DV25 512K x CY7C1383DV25 1MxDescription Pin DefinitionsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 NameCY7C1383DV25, CY7C1383FV25 Pin Definitions continuedFunctional Overview CY7C1381DV25, CY7C1381FV25Address ZZ Mode Electrical CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Interleaved Burst Address Table MODE = Floating or VDDTruth Table 4, 5, 6, 7 CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Truth Table for Read/Write Truth Table for Read/Write 4CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Disabling the JTAG Feature TAP Controller State DiagramTAP Controller Block Diagram IEEE 1149.1 Serial Boundary Scan JTAGTAP Instruction Set CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Reserved TAP AC Switching CharacteristicsTAP Timing CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Scan Register Sizes 2.5V TAP AC Test Conditions2.5V TAP AC Output Load Equivalent Identification Register DefinitionsCY7C1383DV25, CY7C1383FV25 Identification Codes119-Ball BGA Boundary Scan Order 13 CY7C1381DV25, CY7C1381FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 165-Ball BGA Boundary Scan Order 1315. Bit #89 is preset HIGH Ambient Temperature Electrical CharacteristicsMaximum Ratings Operating RangeCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 CapacitanceThermal Resistance AC Test Loads and WaveformsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Switching Characteristics+ Feedback Timing DiagramsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Read Cycle TimingData in D Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 + FeedbackPage 22 of Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Read/Write Cycle Timing 25, 27Page 23 of Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 ZZ Mode Timing 29CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Ordering Information+ Feedback Package DiagramsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Figure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm+ Feedback Package Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Figure 2. 119-Ball BGA 14 x 22 x 2.4 mm165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D Package Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Figure 3. 165-Ball FBGA 13 x 15 x 1.4 mmFlow-Through SRAM Document Number Document History PageIssue Date CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25