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Cypress manual CY7C1381DV25, CY7C1381FV25, CY7C1383DV25, CY7C1383FV25, + Feedback

Models: CY7C1383DV25 CY7C1381FV25 CY7C1381DV25 CY7C1383FV25

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CY7C1381DV25, CY7C1381FV25

			CY7C1381DV25, CY7C1381FV25
			CY7C1383DV25, CY7C1383FV25
Logic Block Diagram – CY7C1381DV25/CY7C1381FV25 [3] (512K x 36)
A0, A1, A		ADDRESS
A0, A1, A		REGISTER
		REGISTER
MODE			A[1:0]
MODE
ADV		BURST	Q1
		BURST
CLK		COUNTER
		AND LOGIC	Q0
	CLR		Q0
	CLR
ADSC
ADSP
	DQ D, DQP D		DQ D, DQP D
BW D	DQ D, DQP D		BYTE
BW D	BYTE		BYTE
	BYTE		WRITE REGISTER
	WRITE REGISTER		WRITE REGISTER
	WRITE REGISTER
	DQ C , DQP C		DQ C , DQP C
BW C	DQ C , DQP C
BW C
	WRITE REGISTER		WRITE REGISTER	MEMORY		OUTPUT	DQs
	WRITE REGISTER			MEMORY	SENSE	OUTPUT	DQs
				ARRAY	SENSE	BUFFERS	DQP A
			DQ B , DQP B	ARRAY	AMPS	BUFFERS	DQP A
	DQ B , DQP B		DQ B , DQP B		AMPS		DQP B
BW B	DQ B , DQP B						DQP B
BW B			WRITE REGISTER				DQP C
							DQP C
							DQP D
	WRITE REGISTER						DQP D
			DQ A, DQP
BW A	DQ A, DQP A		BYTE
BW A	BYTE		WRITE REGISTER
BWE	BYTE		WRITE REGISTER
BWE	WRITE REGISTER
	WRITE REGISTER
GW							INPUT
CE1	ENABLE						REGISTERS
	ENABLE
	REGISTER
CE2	REGISTER
CE2
CE3
OE
	SLEEP

Logic Block Diagram – CY7C1383DV25/CY7C1383FV25 [3] (1M x 18)

A0,A1,A	ADDRESS
A0,A1,A	REGISTER
	REGISTER
MODE			A[1:0]
MODE
ADV		BURST	Q1
		COUNTER AND
			Q0
	DQ B ,DQP	B	DQ B ,DQP B
	DQ B ,DQP	B	WRITE DRIVER
BW B			WRITE DRIVER		OUTPUT
BW B			MEMORY	SENSE	OUTPUT	DQs
			ARRAY	SENSE	BUFFERS	DQs
			ARRAY	AMPS		DQP A
				AMPS		DQP A
	DQ A,DQP A		DQ A,DQP A			DQP B
	DQ A,DQP A		WRITE DRIVER
BW A			WRITE DRIVER
BW A
BWE						INPUT
GW						INPUT
GW	ENABLE					REGISTERS
CE	ENABLE					REGISTERS
CE	1
CE 2
CE 3
OE
	SLEEP
	CONTROL
Note
3. CY7C1381FV25 and CY7C1383FV25 have only 1 chip enable (CE1).
Document #: 38-05547 Rev. *E						Page 2 of 28

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Cypress CY7C1381DV25, CY7C1381FV25, CY7C1383DV25, CY7C1383FV25, Logic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M x

Contents

Selection Guide FeaturesCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Functional DescriptionCY7C1381DV25, CY7C1381FV25 Logic Block Diagram - CY7C1381DV25/CY7C1381FV25 3 512K xLogic Block Diagram - CY7C1383DV25/CY7C1383FV25 3 1M x CY7C1383DV25, CY7C1383FV25CY7C1381DV25 Pin Configurations 100-pin TQFP Pinout 3 Chip EnableCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 512K xCY7C1383FV25 1M x Pin Configurations continued 119-Ball BGA PinoutCY7C1381FV25 512K x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25CY7C1383DV25 1Mx Pin Configurations continued 165-Ball FBGA Pinout3 Chip EnableCY7C1381DV25 512K x CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Name Pin DefinitionsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 DescriptionCY7C1381DV25, CY7C1381FV25 Pin Definitions continuedFunctional Overview CY7C1383DV25, CY7C1383FV25Interleaved Burst Address Table MODE = Floating or VDD ZZ Mode Electrical CharacteristicsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 AddressCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Truth Table 4, 5, 6, 7Truth Table for Read/Write Truth Table for Read/Write 4CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 IEEE 1149.1 Serial Boundary Scan JTAG TAP Controller State DiagramTAP Controller Block Diagram Disabling the JTAG FeatureCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 TAP Instruction SetCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 TAP AC Switching CharacteristicsTAP Timing ReservedIdentification Register Definitions 2.5V TAP AC Test Conditions2.5V TAP AC Output Load Equivalent Scan Register SizesCY7C1381DV25, CY7C1381FV25 Identification Codes119-Ball BGA Boundary Scan Order 13 CY7C1383DV25, CY7C1383FV25CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 165-Ball BGA Boundary Scan Order 1315. Bit #89 is preset HIGH Operating Range Electrical CharacteristicsMaximum Ratings Ambient TemperatureAC Test Loads and Waveforms CapacitanceThermal Resistance CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Switching Characteristics CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Read Cycle Timing Timing DiagramsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 + Feedback+ Feedback Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Data in DRead/Write Cycle Timing 25, 27 Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Page 22 ofZZ Mode Timing 29 Timing Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Page 23 ofOrdering Information CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25Figure 1. 100-Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 + FeedbackFigure 2. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 + FeedbackFigure 3. 165-Ball FBGA 13 x 15 x 1.4 mm Package Diagrams continuedCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165DCY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 Document History PageIssue Date Flow-Through SRAM Document Number