Motorola MC9S12DG128B Modes of Operation, Overview, Chip Configuration Summary, 1 Mode Selection

MC9S12DT128B Device User Guide — V01.07

Section 4 Modes of Operation

4.1 Overview

Eight possible modes determine the operating configuration of the MC9S12DT128B. Each mode has an associated default memory map and external bus configuration controlled by a further pin.

Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.

Table 4-1 Mode Selection

BKGD =	PE6 =	PE5 =	PK7 =	ROMON	Mode Description
MODC	MODB	MODA	ROMCTL	Bit
					Special Single Chip, BDM allowed and ACTIVE. BDM is
0	0	0	X	1	allowed in all other modes but a serial command is
					required to make BDM active.
0	0	1	X	0	Emulation Expanded Narrow, BDM allowed
0	1	0	X	0	Special Test (Expanded Wide), BDM allowed
0	1	1	X	0	Emulation Expanded Wide, BDM allowed
1	0	0	X	1	Normal Single Chip, BDM allowed
1	0	1	0	0	Normal Expanded Narrow, BDM allowed
			1	1
1	1	0	X	1	Special Peripheral; BDM allowed but bus operations
					would cause bus conflicts (must not be used)
1	1	1	0	0	Normal Expanded Wide, BDM allowed
			1	1

For further explanation on the modes refer to the Core User Guide.

Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS	Description
1	Colpitts Oscillator selected
0	Pierce Oscillator/external clock selected

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