Bftident, Bftlen, BFTDATA0, Bfrident | Motorola MC9S12DT128B

MC9S12DT128B Device User Guide — V01.07

	$0300 - $035F			Byteﬂight

	Address	Name		Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	$0315	Reserved	Read:	0	0	0	0	0	0	0	0
	$0315	for Test	Write:
		for Test	Write:
	$0316	Reserved	Read:	0	0	0	0	0	0	0	0
	$0316	for Test	Write:
		for Test	Write:
	$0317	Reserved	Read:	0	0	0	0	0	0	0	0
	$0317	for Test	Write:
		for Test	Write:
	$0318	Reserved	Read:	0	0	0	0	0	0	0	0
	$0318	for Test	Write:
		for Test	Write:
	$0319	Reserved	Read:	0	0	0	0	0	0	0	0
	$0319	for Test	Write:
		for Test	Write:
	$031A	Reserved	Read:	0	0	0	0	0	0	0	0
	$031A	for Test	Write:
		for Test	Write:
	$031B	Reserved	Read:	0	0	0	0	0	0	0	0
	$031B	for Test	Write:
		for Test	Write:
	$031C	Reserved	Read:	0	0	0	0	0	0	0	0
	$031C	for Test	Write:
		for Test	Write:
	$031D	Reserved	Read:	0	0	0	0	0	0	0	0
	$031D	for Test	Write:
		for Test	Write:
	$031E	Reserved	Read:	0	0	0	0	0	0	0	0
	$031E	for Test	Write:
		for Test	Write:
	$031F	Reserved	Read:	0	0	0	0	0	0	0	0
	$031F	for Test	Write:
		for Test	Write:
	$0320	BFTIDENT	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$0320	BFTIDENT	Write:	Bit 7	6	5	4	3	2	1	Bit 0
			Write:
	$0321	BFTLEN	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$0321	BFTLEN	Write:	Bit 7	6	5	4	3	2	1	Bit 0
			Write:
	$0322 -	BFTDATA0-	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$032D	BFTDATA11	Write:	Bit 7	6	5	4	3	2	1	Bit 0
	$032D	BFTDATA11	Write:
	$032E -	Unimplemente	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$032F	d	Write:	Bit 7	6	5	4	3	2	1	Bit 0
	$032F	d	Write:
	$0330	BFRIDENT	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$0330	BFRIDENT	Write:	Bit 7	6	5	4	3	2	1	Bit 0
			Write:
	$0331	BFRLEN	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$0331	BFRLEN	Write:	Bit 7	6	5	4	3	2	1	Bit 0
			Write:
	$0332 -	BFRDATA0-	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$033D	BFRDATA11	Write:	Bit 7	6	5	4	3	2	1	Bit 0
	$033D	BFRDATA11	Write:
	$033E-	Unimplemente	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$033F	d	Write:	Bit 7	6	5	4	3	2	1	Bit 0
	$033F	d	Write:
	$0340	BFFIDENT	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$0340	BFFIDENT	Write:	Bit 7	6	5	4	3	2	1	Bit 0
			Write:
	$0341	BFFLEN	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$0341	BFFLEN	Write:	Bit 7	6	5	4	3	2	1	Bit 0
			Write:
	$0342 -	BFFDATA0-	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$034D	BFFDATA11	Write:	Bit 7	6	5	4	3	2	1	Bit 0
	$034D	BFFDATA11	Write:
	$034E -	Unimplemente	Read:	Bit 7	6	5	4	3	2	1	Bit 0
	$034F	d	Write:	Bit 7	6	5	4	3	2	1	Bit 0
	$034F	d	Write:
	$0350 -	BFBUFCTL0 -	Read:	IFLG	IENA	LOCK	ABTAK	ABTRQ	0	0	CFG
	$035F	BFBUFCTL15	Write:	IFLG	IENA	LOCK		ABTRQ			CFG
	$035F	BFBUFCTL15	Write:

44

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Image 44

Motorola MC9S12DT128B Bftident, Bftlen, BFTDATA0, Bfrident, BFRDATA0, Bffident, Bfflen, BFFDATA0, BFBUFCTL0, BFBUFCTL15

Contents

Original Release Date 18 June Revised 16 Aug Motorola, Inc Revision History Table of Contents MC9S12DT128B Device User Guide Resets and Interrupts System Clock DescriptionModes of Operation HCS12 Core Block Description Clock and Reset Generator CRG Block Description Appendix B Package Information MC9S12DT128B Device User Guide List of Figures Order Partnumber Example MC9S12DT128B Device User Guide List of Tables MC9S12DT128B Device User Guide Modules MC9S12DT128B MC9S12DG128B MC9S12DJ128B MC9S12DB128B PrefaceDerivative Differences1 Document References User Guide Version Document Order Number Overview FeaturesIntroduction MC9S12DT128B Device User Guide Modes of Operation Block Diagram 1shows a block diagram of the MC9S12DT128B device MC9S12DT128B Block Diagram Device Memory Map Device Memory MapAddress Module Size Bytes Core MEMSIZ, IRQ, Hprio MC9S12DT128B Memory Map $0010 $0014 MMC map 1 of 4 Core User Guide Detailed Register Map$0000 $000F Mebi map 1 of 3 Core User Guide $0015 $0016 INT map 1 of 2 Core User Guide $0017 $0017 MMC map 2 of 4 Core User Guide$001E $001E Mebi map 2 of 3 Core User Guide $001F $001F INT map 2 of 2 Core User Guide $0020 $0027Reserved $0028 $002F BKP Core User Guide$0030 $0031 MMC map 4 of 4 Core User Guide $0032 $0033 Mebi map 3 of 3 Core User Guide $0034 $003F CRG Clock and Reset Generator $0040 $007F ECT Enhanced Capture Timer 16 Bit 8 Channels TCTL3 EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4ATCTL4 EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Mcctl Mczi Modmc Rdmcl Mcen MCPR1 MCPR0Flmc Mcflg Ascif Adpu Affc Awai Etrigle Etrigp AscieFifo FRZ1 FRZ0 SRES8 SMP1 SMP0 $00A0 $00C7 PWM Pulse Width Modulator 8 Bit 8 Channel Pwmsclb PwmscntaPwmscntb PWMCNT0 SCI0 Asynchronous Serial Interface $00D0 $00D7 SCI1 Asynchronous Serial Interface SPI0 Serial Peripheral Interface $00E0 $00E7 IIC Inter IC Bus $00F8 $00FFReserved $00E8 $00EF Bdlc Byte Level Data Link Controller J1850$00F0 $00F7 SPI1 Serial Peripheral Interface $0100 $010F Flash Control Register fts128k2 $0110 $011B Eeprom Control Register eets2k $011C $011F Reserved for RAM Control Register EaddrloATD1TEST0 ATD1TEST1 $0140 $017F CAN0 Motorola Scalable can Mscan CAN0TFLG TXE2 TXE1 TXE0CAN0TIER TXEIE2 TXEIE1 TXEIE0 $0180 $01BF CAN1 Motorola Scalable can Mscan $01C0 $01FFReserved $0200 $023FReserved $0240 $027F PIM Port Integration Module Ptip PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0Perp PERP7 $0280 $02BF CAN4 Motorola Scalable can Mscan $02C0 $02FFReserved $0300 $035F Byteﬂight Bftident BftlenBFTDATA0 Bfrident Part ID Assignments $0360 $03FFReservedAssigned Part ID Numbers Memory size registers MC9S12DT128B Device User Guide Signal Description Device Pinout PAD14/AN14 IOC0/PT0 Signal Properties Summary Signal PropertiesPin Name Description PE1 IRQ Vddr PM3 Txbf TXCAN1 TXCAN0 SS0 Vddx Ppsm SPI0 PermPM2 Rxbf RXCAN1 RXCAN0 MISO0 Vddx CAN1, CAN0, Miso Detailed Signal Descriptions EXTAL, Xtal Oscillator PinsReset External Reset Pin Test Test Pin 7 PAD148 / AN160 Port AD Input Pins 9 PAD60 / AN060 Port AD Input Pins10 PA70 / ADDR158 / DATA158 Port a I/O Pins 11 PB70 / ADDR70 / DATA70 Port B I/O Pins Colpitts Oscillator Connections PE7=1 Pierce Oscillator Connections PE7=0 13 PE6 / Modb / IPIPE1 Port E I/O Pin 14 PE5 / Moda / IPIPE0 Port E I/O Pin15 PE4 / Eclk Port E I/O Pin 16 PE3 / Lstrb / Taglo Port E I/O Pin 21 PH6 / KWH6 Port H I/O Pin 22 PH5 / KWH5 Port H I/O Pin23 PH4 / KWH4 Port H I/O Pin 24 PH3 / KWH3 / SS1 Port H I/O Pin 30 PJ10 / KWJ10 Port J I/O Pins 32 PK50 / XADDR1914 Port K I/O Pins29 PJ6 / KWJ6 / RXCAN4 / SDA Port J I/O Pin 31 PK7 / ECS / Romctl Port K I/O Pin 36 PM4 / Bfpsyn / RXCAN0 / RXCAN4/ MOSI0 Port M I/O Pin 37 PM3 / Txbf / TXCAN1 / TXCAN0 / SS0 Port M I/O Pin38 PM2 / Rxbf / RXCAN1 / RXCAN0 / MISO0 Port M I/O Pin 39 PM1 / TXCAN0 / TXB Port M I/O Pin 43 PP5 / KWP5 / PWM5 Port P I/O Pin 44 PP4 / KWP4 / PWM4 Port P I/O Pin45 PP3 / KWP3 / PWM3 / SS1 Port P I/O Pin 46 PP2 / KWP2 / PWM2 / SCK1 Port P I/O Pin Power Supply Pins Vssa VDDX,VSSX Power & Ground Pins for I/O Drivers3 VDD1, VDD2, VSS1, VSS2 Core Power Pins VDDA, Vssa Power Supply Pins for ATD and Vreg 5 VRH, VRL ATD Reference Voltage Input PinsVDDPLL, Vsspll Power Supply Pins for PLL Vregen On Chip Voltage Regulator Enable MC9S12DT128B Device User Guide System Clock Description Clock Connections MC9S12DT128B Device User Guide Chip Configuration Summary Mode SelectionModes of Operation Clock Selection Based on PE7 Operation of the Secured Microcontroller SecuritySecuring the Microcontroller Low Power Modes MC9S12DT128B Device User Guide Resets and Interrupts VectorsVector Table Interrupt Vector Locations Effects of Reset 1 I/O pins Memory MC9S12DT128B Device User Guide Clock and Reset Generator CRG Block Description Enhanced Capture Timer ECT Block DescriptionHCS12 Core Block Description Analog to Digital Converter ATD Block Description Description Serial Peripheral Interface SPI Block DescriptionJ1850 Bdlc Block Description Byteflight BF Block Description RAM Block Description Mscan Block DescriptionPort Integration Module PIM Block Description Voltage Regulator Vreg Block Description Component Purpose Type Value Printed Circuit Board Layout ProposalSuggested External Component Values Recommended PCB Layout for 112LQFP Colpitts Oscillator Recommended PCB Layout for 80QFP Colpitts Oscillator Recommended PCB Layout for 112LQFP Pierce Oscillator Recommended PCB Layout for 80QFP Pierce Oscillator Appendix a Electrical Characteristics Power SupplyGeneral Parameter Classification Pins Current Injection Num Rating Symbol Min Max Unit Absolute Maximum RatingsESD Protection and Latch-up Immunity Table A-1 Absolute Maximum Ratings1 Table A-3 ESD and Latch-Up Protection Characteristics Model Description Symbol Value UnitOperating Conditions Table A-2 ESD and Latch-up Test Conditions Table A-4 Operating Conditions Power Dissipation and Thermal CharacteristicsRating Symbol Min Typ Max Unit Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda Num Rating Symbol Min Typ Max Unit 9 I/O CharacteristicsTable A-5 Thermal Package Characteristics1 Table A-6 5V I/O Characteristics Additional Remarks Supply CurrentsMeasurement Conditions Table A-7 Supply Current Characteristics ATD Characteristics ATD Operating CharacteristicsTable A-8 ATD Operating Characteristics Factors influencing accuracy Current injection Table A-9 ATD Electrical CharacteristicsSource capacitance ATD accuracy Table A-10 ATD Conversion Performance Figure A-1 ATD Accuracy Definitions NVM, Flash and Eeprom NVM timingSingle Word Programming Burst Programming Table A-11 NVM Timing Characteristics Sector EraseMass Erase Blank Check Num Rating Cycles Data Retention Unit Lifetime Table A-12 NVM Reliability CharacteristicsNVM Reliability 100 Voltage Regulator Table A-13 Voltage Regulator Recommended Load Capacitances 102 Reset, Oscillator and PLL Startup Oscillator Pseudo Stop and Wait RecoveryTable A-15 Oscillator Characteristics XFC Component Selection Phase Locked LoopXFC Pin ⋅ synr + Jitter Information = max ⎜ ⋅ t nom Table A-16 PLL Characteristics Table A-17 Mscan Wake-up Pulse Characteristics Mscan 110 Master Mode Mosi Port Data LSB Master LSB OUT Slave Mode Table A-19 SPI Slave Mode Timing Characteristics External Bus Timing General Muxed Bus Timing ECS PK7 PE2 Lstrb PE3 Noacc PE7 PIPO0 Eclk PE4PA, PB Table A-20 Expanded Bus Timing Characteristics Pweh 118 Appendix B Package Information 112-pin Lqfp mechanical dimensions case no 112-pin Lqfp package 80-pin QFP Mechanical Dimensions case no B 80-pin QFP package 122 User Guide End Sheet 124