Motorola MC9S12DB128B, MC9S12DT128B, MC9S12DJ128B Table A-20 Expanded Bus Timing Characteristics

MC9S12DT128B Device User Guide — V01.07

Table A-20 Expanded Bus Timing Characteristics

Conditions are shown in Table A-4unless otherwise noted, CLOAD = 50pF

Num

C

Rating

Symbol

Min

Typ

Max

Unit

1

P

Frequency of operation (E-clock)

fo

0

25.0

MHz

2

P

Cycle time

tcyc

40

ns

3

D

Pulse width, E low

PWEL

19

ns

4

D

Pulse width, E high1

PWEH

19

ns

5

D

Address delay time

tAD

8

ns

6

D

Address valid time to E rise (PWEL–tAD)

tAV

11

ns

7

D

Muxed address hold time

tMAH

2

ns

8

D

Address hold to data valid

tAHDS

7

ns

9

D

Data hold to address

tDHA

2

ns

10

D

Read data setup time

tDSR

13

ns

11

D

Read data hold time

tDHR

0

ns

12

D

Write data delay time

tDDW

7

ns

13

D

Write data hold time

tDHW

2

ns

14

D

Write data setup time(1) (PW

–t

)

tDSW

12

ns

EH

DDW

15

D

Address access time(1) (t

–t

AD

–t

DSR

)

tACCA

19

ns

cyc

16

D

E high access time(1) (PW

EH

–t

DSR

)

tACCE

6

ns

17

D

Non-multiplexed address delay time

tNAD

6

ns

18

D

Non-muxed address valid to E rise (PWEL–tNAD)

tNAV

15

ns

19

D

Non-multiplexed address hold time

tNAH

2

ns

20

D

Chip select delay time

tCSD

16

ns

21

D

Chip select access time(1) (t

–t

–t

DSR

)

tACCS

11

ns

cyc

CSD

22

D

Chip select hold time

tCSH

2

ns

23

D

Chip select negated time

tCSN

8

ns

24

D

Read/write delay time

tRWD

7

ns

25

D

Read/write valid time to E rise (PWEL–tRWD)

tRWV

14

ns

26

D

Read/write hold time

tRWH

2

ns

27

D

Low strobe delay time

tLSD

7

ns

28

D

Low strobe valid time to E rise (PWEL–tLSD)

tLSV

14

ns

29

D

Low strobe hold time

tLSH

2

ns

30

D

NOACC strobe delay time

tNOD

7

ns

31

D

NOACC valid time to E rise (PWEL–tNOD)

tNOV

14

ns

117

http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655