PAD14/AN14 | Motorola MC9S12DT128B, MC9S12DB128B, MC9S12DJ128B

MC9S12DT128B Device User Guide — V01.07

					PP4/KWP4/PWM4


						112
	SS1/PWM3/KWP3/PP3			1
SCK1/PWM2/KWP2/PP2				2


MOSI1/PWM1/KWP1/PP1				3


MISO1/PWM0/KWP0/PP0				4


		XADDR17/PK3		5


		XADDR16/PK2		6

		XADDR15/PK1		7


		XADDR14/PK0		8


		IOC0/PT0		9


		IOC1/PT1		10


		IOC2/PT2		11


		IOC3/PT3		12


		VDD1		13


		VSS1		14


		IOC4/PT4		15


		IOC5/PT5		16


		IOC6/PT6		17


		IOC7/PT7		18


		XADDR19/PK5		19


		XADDR18/PK4		20


		KWJ1/PJ1		21


		KWJ0/PJ0		22


	MODC/TAGHI/BKGD			23


	ADDR0/DATA0/PB0			24


	ADDR1/DATA1/PB1			25


	ADDR2/DATA2/PB2			26


	ADDR3/DATA3/PB3			27


	ADDR4/DATA4/PB4			28		29





					ADDR5/DATA5/PB5

PP5/KPW5/PWM5	PP6/KWP6/PWM6	PP7/KWP7/PWM7	PK7/ECS/ROMCTL	VDDX	VSSX	PM0/RXCAN0/RXB	PM1/TXCAN0/TXB	PM2/RX BF/RXCAN1/RXCAN0/MISO0	PM3/TX BF/TXCAN1/TXCAN0/SS0	PM4/BF PSYN/RXCAN0/RXCAN4/MOSI0	PM5/BF PROK/TXCAN0/TXCAN4/SCK0	PJ6/KWJ6/RXCAN4/SDA	PJ7/KWJ7/TXCAN4/SCL	VREGEN	PS7/SS0	PS6/SCK0	PS5/MOSI0	PS4/MISO0	PS3/TXD1	PS2/RXD1	PS1/TXD0	PS0/RXD0	PM6/BF PERR/RXCAN4	PM7/BF PSLM/TXCAN4	VSSA	VRL
111	110	109	108	107	106	105	104	103	102	101	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	VRH
																										84	VRH
																										83	VDDA
																										82	PAD15/AN15/ETRIG1
																										81	PAD07/AN07/ETRIG0
																										80	PAD14/AN14
																										79	PAD06/AN06
																										78	PAD13/AN13
																										77	PAD05/AN05
																										76	PAD12/AN12
																										75	PAD04/AN04
																										74	PAD11/AN11
																										73	PAD03/AN03
																										72	PAD10/AN10
						MC9S12DT128B, MC9S12DG128B,																				71	PAD02/AN02
						MC9S12DJ128B, MC9S12DB128B																				70	PAD09/AN09
											112LQFP															69	PAD01/AN01
																										68	PAD08/AN08
																										67	PAD00/AN00
																										66	VSS2
																										65	VDD2
																										64	PA7/ADDR15/DATA15
																										63	PA6/ADDR14/DATA14
																										62	PA5/ADDR13/DATA13
																										61	PA4/ADDR12/DATA12
																										60	PA3/ADDR11/DATA11
																										59	PA2/ADDR10/DATA10
																										58	PA1/ADDR9/DATA9
30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50	51	52	53	54	55	57	PA0/ADDR8/DATA8
30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50	51	52	53	54	55	56
ADDR6/DATA6/PB6	ADDR7/DATA7/PB7	KWH7/PH7	KWH6/PH6	KWH5/PH5	KWH4/PH4	XCLKS/NOACC/PE7	MODB/IPIPE1/PE6	MODA/IPIPE0/PE5	ECLK/PE4	VSSR	VDDR	RESET	VDDPLL	XFC	VSSPLL	EXTAL	XTAL	TEST	SS1/KWH3/PH3	SCK1/KWH2/PH2	MOSI1/KWH1/PH1	MISO1/KWH0/PH0	LSTRB/TAGLO/PE3	R/W/PE2	IRQ/PE1	XIRQ/PE0

Signals shown in Bold are not available on the 80 Pin Package

Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128B,

MC9S12DJ128B, MC9S12DB128B

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Motorola MC9S12DT128B, MC9S12DB128B, MC9S12DJ128B, MC9S12DG128B manual PAD14/AN14

Contents

Original Release Date 18 June Revised 16 Aug Motorola, Inc Revision History Table of Contents MC9S12DT128B Device User Guide Resets and Interrupts System Clock DescriptionModes of Operation HCS12 Core Block Description Clock and Reset Generator CRG Block Description Appendix B Package Information MC9S12DT128B Device User Guide List of Figures Order Partnumber Example MC9S12DT128B Device User Guide List of Tables MC9S12DT128B Device User Guide Preface Derivative Differences1Modules MC9S12DT128B MC9S12DG128B MC9S12DJ128B MC9S12DB128B Document References User Guide Version Document Order Number Features IntroductionOverview MC9S12DT128B Device User Guide Modes of Operation Block Diagram 1shows a block diagram of the MC9S12DT128B device MC9S12DT128B Block Diagram Device Memory Map Device Memory MapAddress Module Size Bytes Core MEMSIZ, IRQ, Hprio MC9S12DT128B Memory Map Detailed Register Map $0000 $000F Mebi map 1 of 3 Core User Guide$0010 $0014 MMC map 1 of 4 Core User Guide $0015 $0016 INT map 1 of 2 Core User Guide $0017 $0017 MMC map 2 of 4 Core User Guide$001E $001E Mebi map 2 of 3 Core User Guide $001F $001F INT map 2 of 2 Core User Guide $0020 $0027Reserved $0028 $002F BKP Core User Guide$0030 $0031 MMC map 4 of 4 Core User Guide $0032 $0033 Mebi map 3 of 3 Core User Guide $0034 $003F CRG Clock and Reset Generator $0040 $007F ECT Enhanced Capture Timer 16 Bit 8 Channels TCTL3 EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4ATCTL4 EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Mcctl Mczi Modmc Rdmcl Mcen MCPR1 MCPR0Flmc Mcflg Ascif Adpu Affc Awai Etrigle Etrigp AscieFifo FRZ1 FRZ0 SRES8 SMP1 SMP0 $00A0 $00C7 PWM Pulse Width Modulator 8 Bit 8 Channel Pwmsclb PwmscntaPwmscntb PWMCNT0 SCI0 Asynchronous Serial Interface $00D0 $00D7 SCI1 Asynchronous Serial Interface SPI0 Serial Peripheral Interface $00E0 $00E7 IIC Inter IC Bus $00E8 $00EF Bdlc Byte Level Data Link Controller J1850 $00F0 $00F7 SPI1 Serial Peripheral Interface$00F8 $00FFReserved $0100 $010F Flash Control Register fts128k2 $0110 $011B Eeprom Control Register eets2k $011C $011F Reserved for RAM Control Register EaddrloATD1TEST0 ATD1TEST1 $0140 $017F CAN0 Motorola Scalable can Mscan CAN0TFLG TXE2 TXE1 TXE0CAN0TIER TXEIE2 TXEIE1 TXEIE0 $0180 $01BF CAN1 Motorola Scalable can Mscan $01C0 $01FFReserved $0200 $023FReserved $0240 $027F PIM Port Integration Module Ptip PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0Perp PERP7 $0280 $02BF CAN4 Motorola Scalable can Mscan $02C0 $02FFReserved $0300 $035F Byteﬂight Bftident BftlenBFTDATA0 Bfrident Part ID Assignments $0360 $03FFReservedAssigned Part ID Numbers Memory size registers MC9S12DT128B Device User Guide Signal Description Device Pinout PAD14/AN14 IOC0/PT0 Signal Properties Summary Signal PropertiesPin Name Description PE1 IRQ Vddr PM3 Txbf TXCAN1 TXCAN0 SS0 Vddx Ppsm SPI0 PermPM2 Rxbf RXCAN1 RXCAN0 MISO0 Vddx CAN1, CAN0, Miso Detailed Signal Descriptions EXTAL, Xtal Oscillator PinsReset External Reset Pin Test Test Pin 7 PAD148 / AN160 Port AD Input Pins 9 PAD60 / AN060 Port AD Input Pins10 PA70 / ADDR158 / DATA158 Port a I/O Pins 11 PB70 / ADDR70 / DATA70 Port B I/O Pins Colpitts Oscillator Connections PE7=1 Pierce Oscillator Connections PE7=0 13 PE6 / Modb / IPIPE1 Port E I/O Pin 14 PE5 / Moda / IPIPE0 Port E I/O Pin15 PE4 / Eclk Port E I/O Pin 16 PE3 / Lstrb / Taglo Port E I/O Pin 21 PH6 / KWH6 Port H I/O Pin 22 PH5 / KWH5 Port H I/O Pin23 PH4 / KWH4 Port H I/O Pin 24 PH3 / KWH3 / SS1 Port H I/O Pin 30 PJ10 / KWJ10 Port J I/O Pins 32 PK50 / XADDR1914 Port K I/O Pins29 PJ6 / KWJ6 / RXCAN4 / SDA Port J I/O Pin 31 PK7 / ECS / Romctl Port K I/O Pin 36 PM4 / Bfpsyn / RXCAN0 / RXCAN4/ MOSI0 Port M I/O Pin 37 PM3 / Txbf / TXCAN1 / TXCAN0 / SS0 Port M I/O Pin38 PM2 / Rxbf / RXCAN1 / RXCAN0 / MISO0 Port M I/O Pin 39 PM1 / TXCAN0 / TXB Port M I/O Pin 43 PP5 / KWP5 / PWM5 Port P I/O Pin 44 PP4 / KWP4 / PWM4 Port P I/O Pin45 PP3 / KWP3 / PWM3 / SS1 Port P I/O Pin 46 PP2 / KWP2 / PWM2 / SCK1 Port P I/O Pin Power Supply Pins VDDX,VSSX Power & Ground Pins for I/O Drivers 3 VDD1, VDD2, VSS1, VSS2 Core Power PinsVssa VDDA, Vssa Power Supply Pins for ATD and Vreg 5 VRH, VRL ATD Reference Voltage Input PinsVDDPLL, Vsspll Power Supply Pins for PLL Vregen On Chip Voltage Regulator Enable MC9S12DT128B Device User Guide System Clock Description Clock Connections MC9S12DT128B Device User Guide Chip Configuration Summary Mode SelectionModes of Operation Clock Selection Based on PE7 Security Securing the MicrocontrollerOperation of the Secured Microcontroller Low Power Modes MC9S12DT128B Device User Guide Resets and Interrupts VectorsVector Table Interrupt Vector Locations Effects of Reset 1 I/O pins Memory MC9S12DT128B Device User Guide Clock and Reset Generator CRG Block Description Enhanced Capture Timer ECT Block DescriptionHCS12 Core Block Description Analog to Digital Converter ATD Block Description Description Serial Peripheral Interface SPI Block DescriptionJ1850 Bdlc Block Description Byteflight BF Block Description RAM Block Description Mscan Block DescriptionPort Integration Module PIM Block Description Voltage Regulator Vreg Block Description Printed Circuit Board Layout Proposal Suggested External Component ValuesComponent Purpose Type Value Recommended PCB Layout for 112LQFP Colpitts Oscillator Recommended PCB Layout for 80QFP Colpitts Oscillator Recommended PCB Layout for 112LQFP Pierce Oscillator Recommended PCB Layout for 80QFP Pierce Oscillator Appendix a Electrical Characteristics Power SupplyGeneral Parameter Classification Pins Current Injection Num Rating Symbol Min Max Unit Absolute Maximum RatingsESD Protection and Latch-up Immunity Table A-1 Absolute Maximum Ratings1 Table A-3 ESD and Latch-Up Protection Characteristics Model Description Symbol Value UnitOperating Conditions Table A-2 ESD and Latch-up Test Conditions Power Dissipation and Thermal Characteristics Rating Symbol Min Typ Max UnitTable A-4 Operating Conditions Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda 9 I/O Characteristics Table A-5 Thermal Package Characteristics1Num Rating Symbol Min Typ Max Unit Table A-6 5V I/O Characteristics Supply Currents Measurement ConditionsAdditional Remarks Table A-7 Supply Current Characteristics ATD Characteristics ATD Operating CharacteristicsTable A-8 ATD Operating Characteristics Factors influencing accuracy Table A-9 ATD Electrical Characteristics Source capacitanceCurrent injection ATD accuracy Table A-10 ATD Conversion Performance Figure A-1 ATD Accuracy Definitions NVM, Flash and Eeprom NVM timingSingle Word Programming Burst Programming Table A-11 NVM Timing Characteristics Sector EraseMass Erase Blank Check Table A-12 NVM Reliability Characteristics NVM ReliabilityNum Rating Cycles Data Retention Unit Lifetime 100 Voltage Regulator Table A-13 Voltage Regulator Recommended Load Capacitances 102 Reset, Oscillator and PLL Startup Pseudo Stop and Wait Recovery Table A-15 Oscillator CharacteristicsOscillator Phase Locked Loop XFC PinXFC Component Selection ⋅ synr + Jitter Information = max ⎜ ⋅ t nom Table A-16 PLL Characteristics Table A-17 Mscan Wake-up Pulse Characteristics Mscan 110 Master Mode Mosi Port Data LSB Master LSB OUT Slave Mode Table A-19 SPI Slave Mode Timing Characteristics External Bus Timing General Muxed Bus Timing Eclk PE4 PA, PBECS PK7 PE2 Lstrb PE3 Noacc PE7 PIPO0 Table A-20 Expanded Bus Timing Characteristics Pweh 118 Appendix B Package Information 112-pin Lqfp mechanical dimensions case no 112-pin Lqfp package 80-pin QFP Mechanical Dimensions case no B 80-pin QFP package 122 User Guide End Sheet 124