ATD accuracy | Motorola MC9S12DG128B, MC9S12DT128B, MC9S12DB128B

MC9S12DT128B Device User Guide — V01.07

A.2.3 ATD accuracy

Table A-10specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance.

Table A-10 ATD Conversion Performance

Conditions are shown in Table A-4unless otherwise noted

VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV

fATDCLK = 2.0MHz

Num	C	Rating	Symbol	Min	Typ	Max	Unit

1	P	10-Bit Resolution	LSB		5		mV

2	P	10-Bit Differential Nonlinearity	DNL	–1		1	Counts

3	P	10-Bit Integral Nonlinearity	INL	–2.5	±1.5	2.5	Counts

4	P	10-Bit Absolute Error1	AE	-3	±2.0	3	Counts
5	P	8-Bit Resolution	LSB		20		mV

6	P	8-Bit Differential Nonlinearity	DNL	–0.5		0.5	Counts

7	P	8-Bit Integral Nonlinearity	INL	–1.0	±0.5	1.0	Counts

8	P	8-Bit Absolute Error(1)	AE	-1.5	±1.0	1.5	Counts

NOTES:

1. These values include the quantization error which is inherently 1/2 count for any A/D converter.

For the following definitions see also Figure A-1.

Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.

( ) Vi –Vi –1 DNL i = ------------------------–1

1LSB

The Integral Non-Linearity (INL) is defined as the sum of all DNLs:

n

INL(n) = ∑ DNL(i) = Vn –V0–n

-------------------

1LSB

i = 1

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Motorola MC9S12DG128B, MC9S12DT128B, MC9S12DB128B, MC9S12DJ128B manual ATD accuracy, Table A-10 ATD Conversion Performance

Contents

Original Release Date 18 June Revised 16 Aug Motorola, Inc Revision History Table of Contents MC9S12DT128B Device User Guide HCS12 Core Block Description Resets and InterruptsSystem Clock Description Modes of Operation Clock and Reset Generator CRG Block Description Appendix B Package Information MC9S12DT128B Device User Guide Order Partnumber Example List of Figures MC9S12DT128B Device User Guide List of Tables MC9S12DT128B Device User Guide Modules MC9S12DT128B MC9S12DG128B MC9S12DJ128B MC9S12DB128B PrefaceDerivative Differences1 User Guide Version Document Order Number Document References Overview FeaturesIntroduction MC9S12DT128B Device User Guide Modes of Operation 1shows a block diagram of the MC9S12DT128B device Block Diagram MC9S12DT128B Block Diagram Core MEMSIZ, IRQ, Hprio Device Memory MapDevice Memory Map Address Module Size Bytes MC9S12DT128B Memory Map $0010 $0014 MMC map 1 of 4 Core User Guide Detailed Register Map$0000 $000F Mebi map 1 of 3 Core User Guide $001F $001F INT map 2 of 2 Core User Guide $0015 $0016 INT map 1 of 2 Core User Guide$0017 $0017 MMC map 2 of 4 Core User Guide $001E $001E Mebi map 2 of 3 Core User Guide $0032 $0033 Mebi map 3 of 3 Core User Guide $0020 $0027Reserved$0028 $002F BKP Core User Guide $0030 $0031 MMC map 4 of 4 Core User Guide $0040 $007F ECT Enhanced Capture Timer 16 Bit 8 Channels $0034 $003F CRG Clock and Reset Generator EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A TCTL3EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A TCTL4 Mcflg McctlMczi Modmc Rdmcl Mcen MCPR1 MCPR0 Flmc SRES8 SMP1 SMP0 AscifAdpu Affc Awai Etrigle Etrigp Ascie Fifo FRZ1 FRZ0 $00A0 $00C7 PWM Pulse Width Modulator 8 Bit 8 Channel PWMCNT0 PwmsclbPwmscnta Pwmscntb $00D0 $00D7 SCI1 Asynchronous Serial Interface SCI0 Asynchronous Serial Interface $00E0 $00E7 IIC Inter IC Bus SPI0 Serial Peripheral Interface $00F8 $00FFReserved $00E8 $00EF Bdlc Byte Level Data Link Controller J1850$00F0 $00F7 SPI1 Serial Peripheral Interface $0110 $011B Eeprom Control Register eets2k $0100 $010F Flash Control Register fts128k2 ATD1TEST1 $011C $011F Reserved for RAM Control RegisterEaddrlo ATD1TEST0 $0140 $017F CAN0 Motorola Scalable can Mscan TXEIE2 TXEIE1 TXEIE0 CAN0TFLGTXE2 TXE1 TXE0 CAN0TIER $0180 $01BF CAN1 Motorola Scalable can Mscan $0200 $023FReserved $01C0 $01FFReserved $0240 $027F PIM Port Integration Module PERP7 PtipPTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 Perp $0280 $02BF CAN4 Motorola Scalable can Mscan $0300 $035F Byteﬂight $02C0 $02FFReserved Bfrident BftidentBftlen BFTDATA0 Memory size registers Part ID Assignments$0360 $03FFReserved Assigned Part ID Numbers MC9S12DT128B Device User Guide Device Pinout Signal Description PAD14/AN14 IOC0/PT0 Description Signal Properties SummarySignal Properties Pin Name PE1 IRQ Vddr CAN1, CAN0, Miso PM3 Txbf TXCAN1 TXCAN0 SS0 VddxPpsm SPI0 Perm PM2 Rxbf RXCAN1 RXCAN0 MISO0 Vddx Test Test Pin Detailed Signal DescriptionsEXTAL, Xtal Oscillator Pins Reset External Reset Pin 11 PB70 / ADDR70 / DATA70 Port B I/O Pins 7 PAD148 / AN160 Port AD Input Pins9 PAD60 / AN060 Port AD Input Pins 10 PA70 / ADDR158 / DATA158 Port a I/O Pins Pierce Oscillator Connections PE7=0 Colpitts Oscillator Connections PE7=1 16 PE3 / Lstrb / Taglo Port E I/O Pin 13 PE6 / Modb / IPIPE1 Port E I/O Pin14 PE5 / Moda / IPIPE0 Port E I/O Pin 15 PE4 / Eclk Port E I/O Pin 24 PH3 / KWH3 / SS1 Port H I/O Pin 21 PH6 / KWH6 Port H I/O Pin22 PH5 / KWH5 Port H I/O Pin 23 PH4 / KWH4 Port H I/O Pin 31 PK7 / ECS / Romctl Port K I/O Pin 30 PJ10 / KWJ10 Port J I/O Pins32 PK50 / XADDR1914 Port K I/O Pins 29 PJ6 / KWJ6 / RXCAN4 / SDA Port J I/O Pin 39 PM1 / TXCAN0 / TXB Port M I/O Pin 36 PM4 / Bfpsyn / RXCAN0 / RXCAN4/ MOSI0 Port M I/O Pin37 PM3 / Txbf / TXCAN1 / TXCAN0 / SS0 Port M I/O Pin 38 PM2 / Rxbf / RXCAN1 / RXCAN0 / MISO0 Port M I/O Pin 46 PP2 / KWP2 / PWM2 / SCK1 Port P I/O Pin 43 PP5 / KWP5 / PWM5 Port P I/O Pin44 PP4 / KWP4 / PWM4 Port P I/O Pin 45 PP3 / KWP3 / PWM3 / SS1 Port P I/O Pin Power Supply Pins Vssa VDDX,VSSX Power & Ground Pins for I/O Drivers3 VDD1, VDD2, VSS1, VSS2 Core Power Pins Vregen On Chip Voltage Regulator Enable VDDA, Vssa Power Supply Pins for ATD and Vreg5 VRH, VRL ATD Reference Voltage Input Pins VDDPLL, Vsspll Power Supply Pins for PLL MC9S12DT128B Device User Guide Clock Connections System Clock Description MC9S12DT128B Device User Guide Clock Selection Based on PE7 Chip Configuration SummaryMode Selection Modes of Operation Operation of the Secured Microcontroller SecuritySecuring the Microcontroller Low Power Modes MC9S12DT128B Device User Guide Interrupt Vector Locations Resets and InterruptsVectors Vector Table 1 I/O pins Effects of Reset Memory MC9S12DT128B Device User Guide Analog to Digital Converter ATD Block Description Clock and Reset Generator CRG Block DescriptionEnhanced Capture Timer ECT Block Description HCS12 Core Block Description Byteflight BF Block Description DescriptionSerial Peripheral Interface SPI Block Description J1850 Bdlc Block Description Voltage Regulator Vreg Block Description RAM Block DescriptionMscan Block Description Port Integration Module PIM Block Description Component Purpose Type Value Printed Circuit Board Layout ProposalSuggested External Component Values Recommended PCB Layout for 112LQFP Colpitts Oscillator Recommended PCB Layout for 80QFP Colpitts Oscillator Recommended PCB Layout for 112LQFP Pierce Oscillator Recommended PCB Layout for 80QFP Pierce Oscillator Parameter Classification Appendix a Electrical CharacteristicsPower Supply General Current Injection Pins Table A-1 Absolute Maximum Ratings1 Num Rating Symbol Min Max UnitAbsolute Maximum Ratings ESD Protection and Latch-up Immunity Table A-2 ESD and Latch-up Test Conditions Table A-3 ESD and Latch-Up Protection CharacteristicsModel Description Symbol Value Unit Operating Conditions Table A-4 Operating Conditions Power Dissipation and Thermal CharacteristicsRating Symbol Min Typ Max Unit Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda Num Rating Symbol Min Typ Max Unit 9 I/O CharacteristicsTable A-5 Thermal Package Characteristics1 Table A-6 5V I/O Characteristics Additional Remarks Supply CurrentsMeasurement Conditions Table A-7 Supply Current Characteristics Factors influencing accuracy ATD CharacteristicsATD Operating Characteristics Table A-8 ATD Operating Characteristics Current injection Table A-9 ATD Electrical CharacteristicsSource capacitance Table A-10 ATD Conversion Performance ATD accuracy Figure A-1 ATD Accuracy Definitions Burst Programming NVM, Flash and EepromNVM timing Single Word Programming Blank Check Table A-11 NVM Timing CharacteristicsSector Erase Mass Erase Num Rating Cycles Data Retention Unit Lifetime Table A-12 NVM Reliability CharacteristicsNVM Reliability 100 Table A-13 Voltage Regulator Recommended Load Capacitances Voltage Regulator 102 Startup Reset, Oscillator and PLL Oscillator Pseudo Stop and Wait RecoveryTable A-15 Oscillator Characteristics XFC Component Selection Phase Locked LoopXFC Pin Jitter Information ⋅ synr + = max ⎜ ⋅ t nom Table A-16 PLL Characteristics Mscan Table A-17 Mscan Wake-up Pulse Characteristics 110 Master Mode LSB Master LSB OUT Mosi Port Data Slave Mode Table A-19 SPI Slave Mode Timing Characteristics General Muxed Bus Timing External Bus Timing ECS PK7 PE2 Lstrb PE3 Noacc PE7 PIPO0 Eclk PE4PA, PB Pweh Table A-20 Expanded Bus Timing Characteristics 118 Appendix B Package Information 112-pin Lqfp package 112-pin Lqfp mechanical dimensions case no 80-pin QFP package 80-pin QFP Mechanical Dimensions case no B 122 User Guide End Sheet 124