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Motorola MC9S12DG128B manual A.3.2 NVM Reliability, Table A-12 NVM Reliability Characteristics

Models: MC9S12DT128B

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A.3.2 NVM Reliability

MC9S12DT128B Device User Guide — V01.07

4.Burst Programming operations are not applicable to EEPROM

5.Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.

6.Minimum time, if first word in the array is not blank

7.Maximum time to complete check on an erased block

A.3.2 NVM Reliability

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures.

The failure rates for data retention and program/erase cycling are specified at the operating conditions noted.

The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed.

NOTE: All values shown in Table A-12are target values and subject to further extensive characterization

Table A-12 NVM Reliability Characteristics

Conditions are shown in Table A-4unless otherwise noted

	Num	C	Rating	Cycles	Data Retention	Unit
	Num	C	Rating	Cycles	Lifetime	Unit
					Lifetime

	1	C	Flash/EEPROM (-40˚C to +125˚C)	10	15	Years

	2	C	EEPROM (-40˚C to +125˚C)	10,000	5	Years

NOTE: Flash cycling performance is 10 cycles at -40˚C to +125˚C. Data retention is specified for 15 years.

NOTE: EEPROM cycling performance is 10K cycles at -40˚C to 125˚C. Data retention is specified for 5 years on words after cycling 10K times. However if only 10 cycles are executed on a word the data retention is specified for 15 years.

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Motorola MC9S12DG128B, MC9S12DT128B, MC9S12DB128B manual A.3.2 NVM Reliability, Table A-12 NVM Reliability Characteristics

Contents

提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User Guide V01.07 Covers alsoMC9S12DG128B, MC9S12DJ128B MC9S12DB128B Original Release Date 18 June Revised 16 Aug Motorola, IncRevision Revision HistoryDOCUMENT NUMBER 9S12DT128BDGV1/D VersionTable of Contents Section 2 Signal DescriptionSection 1 Introduction 2.3.21 PH6 / KWH6 - Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.22 PH5 / KWH5 - Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.23 PH4 / KWH4 - Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.24 PH3 / KWH3 / SS1 - Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.25 PH2 / KWH2 / SCK1 - Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.26 PH1 / KWH1 / MOSI1 - Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.27 PH0 / KWH0 / MISO1 - Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL - PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA - PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.30 PJ10 / KWJ10 - Port J I/O Pins 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.31 PK7 / ECS / ROMCTL - Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.32 PK50 / XADDR1914 - Port K I/O Pins 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.33 PM7 / BFPSLM / TXCAN4 - Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.34 PM6 / BFPERR / RXCAN4 - Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.35 PM5 / BFPROK / TXCAN0 / TXCAN4 / SCK0 - Port M I/O Pin 5 . . . . . . . . . . . . .58 2.3.36 PM4 / BFPSYN / RXCAN0 / RXCAN4/ MOSI0 - Port M I/O Pin 4. . . . . . . . . . . . .59 2.3.37 PM3 / TXBF / TXCAN1 / TXCAN0 / SS0 - Port M I/O Pin 3 . . . . . . . . . . . . . . . . .59 2.3.38 PM2 / RXBF / RXCAN1 / RXCAN0 / MISO0 - Port M I/O Pin 2. . . . . . . . . . . . . . .59 2.3.39 PM1 / TXCAN0 / TXB - Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.40 PM0 / RXCAN0 / RXB - Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.41 PP7 / KWP7 / PWM7 - Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.42 PP6 / KWP6 / PWM6 - Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.43 PP5 / KWP5 / PWM5 - Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.44 PP4 / KWP4 / PWM4 - Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.45 PP3 / KWP3 / PWM3 / SS1 - Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.46 PP2 / KWP2 / PWM2 / SCK1 - Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.47 PP1 / KWP1 / PWM1 / MOSI1 - Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.48 PP0 / KWP0 / PWM0 / MISO1 - Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.49 PS7 / SS0 - Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.50 PS6 / SCK0 - Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.51 PS5 / MOSI0 - Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.52 PS4 / MISO0 - Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.53 PS3 / TXD1 - Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.54 PS2 / RXD1 - Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.55 PS1 / TXD0 - Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.56 PS0 / RXD0 - Port S I/O Pin 0 Section 6 HCS12 Core Block Description Section 5 Resets and InterruptsSection 3 System Clock Description Section 4 Modes of OperationSection 7 Clock and Reset Generator CRG Block Description A.1 General A.1.1 Parameter Classification A.1.2 Power Supply7.1 Device-specific information 7.1.1 XCLKS Appendix B Package Information 提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User GuideList of Figures 提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User GuideList of Tables $01C0 - $01FF Reserved Table 0-1 Derivative Differences1 PrefacePackage Options FU = 80QFP PV = 112LQFP MC9S12 DJ128B C FUPackage Option Temperature Option Device Title Controller Family Temperature Options1.2 Features Section 1 Introduction1.1 Overview Digital filtering Programmable rising or falling edge trigger Memory 1.3 Modes of Operation 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DT128B device提供单片机解密、IC解密、芯片解密业务 010-62245566 提供单片机解密、IC解密、芯片解密业务 010-62245566 Figure 1-1 MC9S12DT128B Block Diagram1.5 Device Memory Map Table 1-1 Device Memory Map提供单片机解密、IC解密、芯片解密业务 010-62245566 $0000 Table 1-1 Device Memory MapFigure 1-2 MC9S12DT128B Memory Map 提供单片机解密、IC解密、芯片解密业务 010-62245566$0010 - $0014 1.5.1 Detailed Register Map$0000 - $000F MEBI map 1 of 3 Core User GuideMMC map 2 of 4 Core User Guide $0015 - $0016INT map 1 of 2 Core User Guide $0017 - $0017$0030 - $0031 $0020 - $0027Reserved$0028 - $002F BKP Core User Guide$0040 - $007F CRG Clock and Reset GeneratorECT Enhanced Capture Timer 16 Bit 8 Channels $0034 - $003F提供单片机解密、IC解密、芯片解密业务 010-62245566 ECT Enhanced Capture Timer 16 Bit 8 Channels$0040 - $007F MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 010-62245566 ECT Enhanced Capture Timer 16 Bit 8 Channels$0040 - $007F MC9S12DT128B Device User GuideATD0 Analog to Digital Converter 10 Bit 8 Channel ECT Enhanced Capture Timer 16 Bit 8 Channels$0040 - $007F $0080 - $009FPWM Pulse Width Modulator 8 Bit 8 Channel $0080 - $009FATD0 Analog to Digital Converter 10 Bit 8 Channel $00A0 - $00C7提供单片机解密、IC解密、芯片解密业务 010-62245566 $00A0 - $00C7PWM Pulse Width Modulator 8 Bit 8 Channel MC9S12DT128B Device User Guide$00D0 - $00D7 $00A0 - $00C7PWM Pulse Width Modulator 8 Bit 8 Channel SCI0 Asynchronous Serial InterfaceIIC Inter IC Bus SCI1 Asynchronous Serial InterfaceSPI0 Serial Peripheral Interface $00E0 - $00E7SPI1 Serial Peripheral Interface $00E8 - $00EFBDLC Byte Level Data Link Controller J1850 $00F0 - $00F7EEPROM Control Register eets2k $0100 - $010FFlash Control Register fts128k2 $0110 - $011BReserved for RAM Control Register $0110 - $011BEEPROM Control Register eets2k $011C - $011FCAN0 Motorola Scalable CAN - MSCAN $0120 - $013FATD1 Analog to Digital Converter 10 Bit 8 Channel $0140 - $017F提供单片机解密、IC解密、芯片解密业务 010-62245566 $0140 - $017FCAN0 Motorola Scalable CAN - MSCAN MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 010-62245566 $0180 - $01BFCAN1 Motorola Scalable CAN - MSCAN MC9S12DT128B Device User Guide$0200 - $023FReserved $0180 - $01BFCAN1 Motorola Scalable CAN - MSCAN $01C0 - $01FFReserved提供单片机解密、IC解密、芯片解密业务 010-62245566 $0240 - $027FPIM Port Integration Module MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 010-62245566 $0240 - $027FPIM Port Integration Module MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 010-62245566 $0280 - $02BFCAN4 Motorola Scalable CAN - MSCAN MC9S12DT128B Device User GuideMC9S12DT128B Device User Guide $02C0 - $02FFReserved$0300 - $035F Byteﬂight提供单片机解密、IC解密、芯片解密业务 010-62245566 $0300 - $035FByteﬂight MC9S12DT128B Device User GuideTable 1-4 Memory size registers 1.6 Part ID Assignments$0360 - $03FFReserved Table 1-3 Assigned Part ID Numbers提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User Guide2.1 Device Pinout Section 2 Signal DescriptionPAD14/AN14 Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128BMC9S12DJ128B, MC9S12DB128B 提供单片机解密、IC解密、芯片解密业务提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User Guide2.2 Signal Properties Summary Signal Properties提供单片机解密、IC解密、芯片解密业务 010-62245566 Function MC9S12DT128B Device User GuidePin Name DescriptionFunction MC9S12DT128B Device User GuideDescription Function2.3.3 TEST - Test Pin 2.3 Detailed Signal Descriptions2.3.1 EXTAL, XTAL - Oscillator Pins 2.3.2 RESET - External Reset Pin2.3.11 PB70 / ADDR70 / DATA70 - Port B I/O Pins 2.3.7 PAD148 / AN160 - Port AD Input Pins2.3.9 PAD60 / AN060 - Port AD Input Pins 2.3.10 PA70 / ADDR158 / DATA158 - Port A I/O Pins提供单片机解密、IC解密、芯片解密业务 010-62245566 Figure 2-4 Colpitts Oscillator Connections PE7=1Figure 2-5 Pierce Oscillator Connections PE7=0 Figure 2-6 External Clock Connections PE7=02.3.16 PE3 / LSTRB / TAGLO - Port E I/O Pin 2.3.13 PE6 / MODB / IPIPE1 - Port E I/O Pin2.3.14 PE5 / MODA / IPIPE0 - Port E I/O Pin 2.3.15 PE4 / ECLK - Port E I/O Pin2.3.24 PH3 / KWH3 / SS1 - Port H I/O Pin 2.3.21 PH6 / KWH6 - Port H I/O Pin2.3.22 PH5 / KWH5 - Port H I/O Pin 2.3.23 PH4 / KWH4 - Port H I/O Pin2.3.31 PK7 / ECS / ROMCTL - Port K I/O Pin 2.3.30 PJ10 / KWJ10 - Port J I/O Pins2.3.32 PK50 / XADDR1914 - Port K I/O Pins 2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA - PORT J I/O Pin2.3.39 PM1 / TXCAN0 / TXB - Port M I/O Pin 2.3.36 PM4 / BFPSYN / RXCAN0 / RXCAN4/ MOSI0 - Port M I/O Pin2.3.37 PM3 / TXBF / TXCAN1 / TXCAN0 / SS0 - Port M I/O Pin 2.3.38 PM2 / RXBF / RXCAN1 / RXCAN0 / MISO0 - Port M I/O Pin2.3.46 PP2 / KWP2 / PWM2 / SCK1 - Port P I/O Pin 2.3.43 PP5 / KWP5 / PWM5 - Port P I/O Pin2.3.44 PP4 / KWP4 / PWM4 - Port P I/O Pin 2.3.45 PP3 / KWP3 / PWM3 / SS1 - Port P I/O Pin2.3.52 PS4 / MISO0 - Port S I/O Pin 2.4 Power Supply Pins2.3.57 PT70 / IOC70 - Port T I/O Pins 2.3.51 PS5 / MOSI0 - Port S I/O PinNOTE No load allowed except for bypass capacitors 2.4.1 VDDX,VSSX - Power & Ground Pins for I/O Drivers2.4.3 VDD1, VDD2, VSS1, VSS2 - Core Power Pins NOTE All VSS pins must be connected together in the application2.4.7 VREGEN - On Chip Voltage Regulator Enable 2.4.4 VDDA, VSSA - Power Supply Pins for ATD and VREG2.4.5 VRH, VRL - ATD Reference Voltage Input Pins 2.4.6 VDDPLL, VSSPLL - Power Supply Pins for PLL提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User GuideSection 3 System Clock Description 3.1 OverviewFigure 3-1 Clock Connections 提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User GuideTable 4-1 Mode Selection 4.2 Chip Configuration SummarySection 4 Modes of Operation 4.1 OverviewTable 4-3 Voltage Regulator VREGEN 4.3 Security4.3.1 Securing the Microcontroller 4.3.2 Operation of the Secured Microcontroller4.4.2 Pseudo Stop 4.4 Low Power Modes4.3.3 Unsecuring the Microcontroller 4.4.1 Stop提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User Guide5.2.1 Vector Table Section 5 Resets and Interrupts5.1 Overview 5.2 Vectors5.3.1 I/O pins 5.3 Effects of ResetThe RAM array is not automatically initialized out of reset 5.3.2 Memory提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User GuideSection 9 Analog to Digital Converter ATD Block Description Section 7 Clock and Reset Generator CRG Block DescriptionSection 8 Enhanced Capture Timer ECT Block Description Section 6 HCS12 Core Block DescriptionSection 14 Byteflight BF Block Description DescriptionSection 12 Serial Peripheral Interface SPI Block Description Section 13 J1850 BDLC Block DescriptionSection 21 Voltage Regulator VREG Block Description Section 18 RAM Block DescriptionSection 19 MSCAN Block Description Section 20 Port Integration Module PIM Block DescriptionTable 22-1 Suggested External Component Values Section 22 Printed Circuit Board Layout Proposal提供单片机解密、IC解密、芯片解密业务 010-62245566 Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator提供单片机解密、IC解密、芯片解密业务 010-62245566 Figure 22-2 Recommended PCB Layout for 80QFP Colpitts OscillatorFigure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator 提供单片机解密、IC解密、芯片解密业务 010-62245566C1 VSS1 Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 010-62245566 A.1.1 Parameter Classification Appendix A Electrical CharacteristicsA.1.2 Power Supply A.1 GeneralVDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and A.1.3 PinsA.1.4 Current Injection A.1.3.1 5V I/O pinsA.1.5 Absolute Maximum Ratings A.1.6 ESD Protection and Latch-up ImmunityTable A-1 Absolute Maximum Ratings1 A.1.7 Operating Conditions Table A-3 ESD and Latch-Up Protection CharacteristicsTable A-2 ESD and Latch-up Test Conditions A.1.8 Power Dissipation and Thermal Characteristics Table A-4 Operating Conditions提供单片机解密、IC解密、芯片解密业务 010-62245566 The total power dissipation can be calculated from A.1.9 I/O Characteristics Table A-5 Thermal Package Characteristics1提供单片机解密、IC解密、芯片解密业务 010-62245566 Table A-6 5V I/O Characteristics 提供单片机解密、IC解密、芯片解密业务 010-622455662. Refer to Section A.1.4 Current Injection, for more details A.1.10 Supply Currents A.1.10.1 Measurement ConditionsA.1.10.2 Additional Remarks 提供单片机解密、IC解密、芯片解密业务 010-62245566 Table A-7 Supply Current CharacteristicsTable A-8 ATD Operating Characteristics A.2 ATD CharacteristicsA.2.1 ATD Operating Characteristics A.2.2 Factors influencing accuracy≥ 1024 * C Table A-9 ATD Electrical CharacteristicsA.2.2.2 Source capacitance A.2.2.3 Current injection1LSB A.2.3 ATD accuracy1LSB INLn = ∑ DNLi = Vn -V0 -nVin mV ResolutionFigure A-1 ATD Accuracy Definitions Vi-1 LSBA.3.1.2 Burst Programming A.3 NVM, Flash and EEPROMA.3.1 NVM timing A.3.1.1 Single Word ProgrammingA.3.1.3 Sector Erase t mass ≈tcheck ≈ location ⋅ tcyc + 10 ⋅ tcyc Table A-11 NVM Timing CharacteristicsTable A-12 NVM Reliability Characteristics A.3.2 NVM Reliability提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User GuideA.4 Voltage Regulator Table A-13 Voltage Regulator Recommended Load Capacitances提供单片机解密、IC解密、芯片解密业务 010-62245566 提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User GuideA.5.1.3 External Reset A.5 Reset, Oscillator and PLLA.5.1 Startup Table A-14 Startup CharacteristicsA.5.2 Oscillator A.5.1.5 Pseudo Stop and Wait RecoveryTable A-15 Oscillator Characteristics KΦ = -ich ⋅ KV A.5.3 Phase Locked LoopXFC Pin K V = K 1 ⋅ eζ + 2 ⋅ ζ ⋅ f ref→ f C ζ =N ⋅ t nom J N = max ⎜N ⋅ t nom JN = j1 + jΔLock Table A-16 PLL Characteristics提供单片机解密、IC解密、芯片解密业务 010-62245566 ΔtrkA.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics提供单片机解密、IC解密、芯片解密业务 010-62245566 提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 010-62245566 A.7 SPIA.7.1 Master Mode Figure A-5 SPI Master Timing CPHA =2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB Table A-18 SPI Master Mode Timing Characteristics1Figure A-6 SPI Master Timing CPHA =1 提供单片机解密、IC解密、芯片解密业务 010-62245566提供单片机解密、IC解密、芯片解密业务 010-62245566 A.7.2 Slave ModeFigure A-7 SPI Slave Timing CPHA = Figure A-8 SPI Slave Timing CPHA =1Rating Table A-19 SPI Slave Mode Timing CharacteristicsSymbol MC9S12DT128B Device User GuideA.8.1 General Muxed Bus Timing A.8 External Bus TimingFigure A-9 General External Bus Timing MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 010-62245566 提供单片机解密、IC解密、芯片解密业务 010-62245566 Table A-20 Expanded Bus Timing CharacteristicsTable A-20 Expanded Bus Timing Characteristics 提供单片机解密、IC解密、芯片解密业务 010-62245566tNOH Appendix B Package Information B.1 General提供单片机解密、IC解密、芯片解密业务 010-62245566 B.2 112-pin LQFP package Figure 22-5 112-pin LQFP mechanical dimensions case no提供单片机解密、IC解密、芯片解密业务 010-62245566 B.3 80-pin QFP package Figure 1 80-pin QFP Mechanical Dimensions case no. 841B提供单片机解密、IC解密、芯片解密业务 010-62245566 提供单片机解密、IC解密、芯片解密业务 010-62245566 MC9S12DT128B Device User GuideUser Guide End Sheet MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 FINAL PAGE OF 124 PAGES MC9S12DT128B Device User Guide提供单片机解密、IC解密、芯片解密业务 010-62245566