Motorola MC9S12DG128B manual A.7 SPI, A.7.1 Master Mode, Figure A-5 SPI Master Timing CPHA =

MC9S12DT128B Device User Guide — V01.07

A.7 SPI

A.7.1 Master Mode

Figure A-5and Figure A-6illustrate the master mode timing. Timing values are shown in Table A-18.

SS1
(OUTPUT)
2		1
SCK		4
(CPOL = 0)
(OUTPUT)		4
SCK
(CPOL = 1)
(OUTPUT)
5	6
MISO	MSB IN2	BIT 6 . . . 1
(INPUT)
9		9

MOSI	MSB OUT2	BIT 6 . . . 1
(OUTPUT)

11	3
12
LSB IN
	10
LSB OUT

1.if configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure A-5 SPI Master Timing (CPHA = 0)

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