Motorola MC9S12DT128B manual Digital filtering Programmable rising or falling edge trigger Memory

MC9S12DT128B Device User Guide — V01.07

–Digital filtering

–Programmable rising or falling edge trigger

•Memory

–128K Flash EEPROM

–2K byte EEPROM

–8K byte RAM

•Two 8-channel Analog-to-Digital Converters

–10-bit resolution

–External conversion trigger capability

•Three 1M bit per second, CAN 2.0 A, B software compatible modules

–Five receive and three transmit buffers

–Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or8 x 8 bit

–Four separate interrupt channels for Rx, Tx, error and wake-up

–Low-pass filter wake-up function

–Loop-back for self test operation

•Enhanced Capture Timer

–16-bit main counter with 7-bit prescaler

–8 programmable input capture or output compare channels

–Two 8-bit or one 16-bit pulse accumulators

•8 PWM channels

–Programmable period and duty cycle

–8-bit 8-channel or 16-bit 4-channel

–Separate control for each pulse width and duty cycle

–Center-aligned or left-aligned outputs

–Programmable clock select logic with a wide range of frequencies

–Fast emergency shutdown input

–Usable as interrupt inputs

•Serial interfaces

–Two asynchronous Serial Communications Interfaces (SCI)

–Two Synchronous Serial Peripheral Interface (SPI)

–Byteflight

•Byte Data Link Controller (BDLC)

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