Original Release Date 18 June Revised 16 Aug Motorola, Inc
MC9S12DT128B Device User Guide V01.07 Covers also
MC9S12DG128B, MC9S12DJ128B MC9S12DB128B
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Version
Revision History
DOCUMENT NUMBER 9S12DT128BDGV1/D
Revision
Section 2 Signal Description
Table of Contents
Section 1 Introduction
2.3.21 PH6 / KWH6 - Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.22 PH5 / KWH5 - Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.23 PH4 / KWH4 - Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.24 PH3 / KWH3 / SS1 - Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.25 PH2 / KWH2 / SCK1 - Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.26 PH1 / KWH1 / MOSI1 - Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.27 PH0 / KWH0 / MISO1 - Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL - PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA - PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.30 PJ10 / KWJ10 - Port J I/O Pins 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.31 PK7 / ECS / ROMCTL - Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.32 PK50 / XADDR1914 - Port K I/O Pins 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.33 PM7 / BFPSLM / TXCAN4 - Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.34 PM6 / BFPERR / RXCAN4 - Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.35 PM5 / BFPROK / TXCAN0 / TXCAN4 / SCK0 - Port M I/O Pin 5 . . . . . . . . . . . . .58 2.3.36 PM4 / BFPSYN / RXCAN0 / RXCAN4/ MOSI0 - Port M I/O Pin 4. . . . . . . . . . . . .59 2.3.37 PM3 / TXBF / TXCAN1 / TXCAN0 / SS0 - Port M I/O Pin 3 . . . . . . . . . . . . . . . . .59 2.3.38 PM2 / RXBF / RXCAN1 / RXCAN0 / MISO0 - Port M I/O Pin 2. . . . . . . . . . . . . . .59 2.3.39 PM1 / TXCAN0 / TXB - Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.40 PM0 / RXCAN0 / RXB - Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.41 PP7 / KWP7 / PWM7 - Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.42 PP6 / KWP6 / PWM6 - Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.43 PP5 / KWP5 / PWM5 - Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.44 PP4 / KWP4 / PWM4 - Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.45 PP3 / KWP3 / PWM3 / SS1 - Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.46 PP2 / KWP2 / PWM2 / SCK1 - Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.47 PP1 / KWP1 / PWM1 / MOSI1 - Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.48 PP0 / KWP0 / PWM0 / MISO1 - Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.49 PS7 / SS0 - Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.50 PS6 / SCK0 - Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.51 PS5 / MOSI0 - Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.52 PS4 / MISO0 - Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.53 PS3 / TXD1 - Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.54 PS2 / RXD1 - Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.55 PS1 / TXD0 - Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.56 PS0 / RXD0 - Port S I/O Pin 0
Section 4 Modes of Operation
Section 5 Resets and Interrupts
Section 3 System Clock Description
Section 6 HCS12 Core Block Description
A.1 General A.1.1 Parameter Classification A.1.2 Power Supply
Section 7 Clock and Reset Generator CRG Block Description
7.1 Device-specific information 7.1.1 XCLKS
Appendix B Package Information
MC9S12DT128B Device User Guide
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List of Figures
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List of Tables
$01C0 - $01FF Reserved
Preface
Table 0-1 Derivative Differences1
MC9S12 DJ128B C FU
Package Option Temperature Option Device Title Controller Family
Temperature Options
Package Options FU = 80QFP PV = 112LQFP
Section 1 Introduction
1.2 Features
1.1 Overview
Digital filtering Programmable rising or falling edge trigger Memory
1.3 Modes of Operation
Figure 1-1 shows a block diagram of the MC9S12DT128B device
1.4 Block Diagram
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Figure 1-1 MC9S12DT128B Block Diagram
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Table 1-1 Device Memory Map
1.5 Device Memory Map
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Table 1-1 Device Memory Map
Figure 1-2 MC9S12DT128B Memory Map
$0000
MEBI map 1 of 3 Core User Guide
1.5.1 Detailed Register Map
$0000 - $000F
$0010 - $0014
$0017 - $0017
$0015 - $0016
INT map 1 of 2 Core User Guide
MMC map 2 of 4 Core User Guide
BKP Core User Guide
$0020 - $0027Reserved
$0028 - $002F
$0030 - $0031
$0034 - $003F
CRG Clock and Reset Generator
ECT Enhanced Capture Timer 16 Bit 8 Channels
$0040 - $007F
MC9S12DT128B Device User Guide
ECT Enhanced Capture Timer 16 Bit 8 Channels
$0040 - $007F
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MC9S12DT128B Device User Guide
ECT Enhanced Capture Timer 16 Bit 8 Channels
$0040 - $007F
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$0080 - $009F
ECT Enhanced Capture Timer 16 Bit 8 Channels
$0040 - $007F
ATD0 Analog to Digital Converter 10 Bit 8 Channel
$00A0 - $00C7
$0080 - $009F
ATD0 Analog to Digital Converter 10 Bit 8 Channel
PWM Pulse Width Modulator 8 Bit 8 Channel
MC9S12DT128B Device User Guide
$00A0 - $00C7
PWM Pulse Width Modulator 8 Bit 8 Channel
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SCI0 Asynchronous Serial Interface
$00A0 - $00C7
PWM Pulse Width Modulator 8 Bit 8 Channel
$00D0 - $00D7
$00E0 - $00E7
SCI1 Asynchronous Serial Interface
SPI0 Serial Peripheral Interface
IIC Inter IC Bus
$00F0 - $00F7
$00E8 - $00EF
BDLC Byte Level Data Link Controller J1850
SPI1 Serial Peripheral Interface
$0110 - $011B
$0100 - $010F
Flash Control Register fts128k2
EEPROM Control Register eets2k
$011C - $011F
$0110 - $011B
EEPROM Control Register eets2k
Reserved for RAM Control Register
$0140 - $017F
$0120 - $013F
ATD1 Analog to Digital Converter 10 Bit 8 Channel
CAN0 Motorola Scalable CAN - MSCAN
MC9S12DT128B Device User Guide
$0140 - $017F
CAN0 Motorola Scalable CAN - MSCAN
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MC9S12DT128B Device User Guide
$0180 - $01BF
CAN1 Motorola Scalable CAN - MSCAN
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$01C0 - $01FFReserved
$0180 - $01BF
CAN1 Motorola Scalable CAN - MSCAN
$0200 - $023FReserved
MC9S12DT128B Device User Guide
$0240 - $027F
PIM Port Integration Module
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MC9S12DT128B Device User Guide
$0240 - $027F
PIM Port Integration Module
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MC9S12DT128B Device User Guide
$0280 - $02BF
CAN4 Motorola Scalable CAN - MSCAN
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Byteflight
$02C0 - $02FFReserved
$0300 - $035F
MC9S12DT128B Device User Guide
MC9S12DT128B Device User Guide
$0300 - $035F
Byteflight
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Table 1-3 Assigned Part ID Numbers
1.6 Part ID Assignments
$0360 - $03FFReserved
Table 1-4 Memory size registers
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Section 2 Signal Description
2.1 Device Pinout
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Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128B
MC9S12DJ128B, MC9S12DB128B
PAD14/AN14
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Signal Properties
2.2 Signal Properties Summary
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Description
MC9S12DT128B Device User Guide
Pin Name
Function
Function
MC9S12DT128B Device User Guide
Description
Function
2.3.2 RESET - External Reset Pin
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL - Oscillator Pins
2.3.5 BKGD / TAGHI / MODC - Background Debug, Tag High, and Mode Pin
2.3.10 PA70 / ADDR158 / DATA158 - Port A I/O Pins
2.3.7 PAD148 / AN160 - Port AD Input Pins
2.3.9 PAD60 / AN060 - Port AD Input Pins
2.3.11 PB70 / ADDR70 / DATA70 - Port B I/O Pins
Figure 2-6 External Clock Connections PE7=0
Figure 2-4 Colpitts Oscillator Connections PE7=1
Figure 2-5 Pierce Oscillator Connections PE7=0
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2.3.15 PE4 / ECLK - Port E I/O Pin
2.3.13 PE6 / MODB / IPIPE1 - Port E I/O Pin
2.3.14 PE5 / MODA / IPIPE0 - Port E I/O Pin
2.3.16 PE3 / LSTRB / TAGLO - Port E I/O Pin
2.3.23 PH4 / KWH4 - Port H I/O Pin
2.3.21 PH6 / KWH6 - Port H I/O Pin
2.3.22 PH5 / KWH5 - Port H I/O Pin
2.3.24 PH3 / KWH3 / SS1 - Port H I/O Pin
2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA - PORT J I/O Pin
2.3.30 PJ10 / KWJ10 - Port J I/O Pins
2.3.32 PK50 / XADDR1914 - Port K I/O Pins
2.3.31 PK7 / ECS / ROMCTL - Port K I/O Pin
2.3.38 PM2 / RXBF / RXCAN1 / RXCAN0 / MISO0 - Port M I/O Pin
2.3.36 PM4 / BFPSYN / RXCAN0 / RXCAN4/ MOSI0 - Port M I/O Pin
2.3.37 PM3 / TXBF / TXCAN1 / TXCAN0 / SS0 - Port M I/O Pin
2.3.39 PM1 / TXCAN0 / TXB - Port M I/O Pin
2.3.45 PP3 / KWP3 / PWM3 / SS1 - Port P I/O Pin
2.3.43 PP5 / KWP5 / PWM5 - Port P I/O Pin
2.3.44 PP4 / KWP4 / PWM4 - Port P I/O Pin
2.3.46 PP2 / KWP2 / PWM2 / SCK1 - Port P I/O Pin
2.3.51 PS5 / MOSI0 - Port S I/O Pin
2.4 Power Supply Pins
2.3.57 PT70 / IOC70 - Port T I/O Pins
2.3.52 PS4 / MISO0 - Port S I/O Pin
NOTE All VSS pins must be connected together in the application
2.4.1 VDDX,VSSX - Power & Ground Pins for I/O Drivers
2.4.3 VDD1, VDD2, VSS1, VSS2 - Core Power Pins
NOTE No load allowed except for bypass capacitors
2.4.6 VDDPLL, VSSPLL - Power Supply Pins for PLL
2.4.4 VDDA, VSSA - Power Supply Pins for ATD and VREG
2.4.5 VRH, VRL - ATD Reference Voltage Input Pins
2.4.7 VREGEN - On Chip Voltage Regulator Enable
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3.1 Overview
Section 3 System Clock Description
Figure 3-1 Clock Connections
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4.1 Overview
4.2 Chip Configuration Summary
Section 4 Modes of Operation
Table 4-1 Mode Selection
4.3.2 Operation of the Secured Microcontroller
4.3 Security
4.3.1 Securing the Microcontroller
4.3.2.1 Normal Single Chip Mode
4.4.1 Stop
4.4 Low Power Modes
4.3.3 Unsecuring the Microcontroller
4.4.2 Pseudo Stop
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5.2 Vectors
Section 5 Resets and Interrupts
5.1 Overview
5.2.1 Vector Table
5.3 Effects of Reset
5.3.1 I/O pins
5.3.2 Memory
The RAM array is not automatically initialized out of reset
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Section 6 HCS12 Core Block Description
Section 7 Clock and Reset Generator CRG Block Description
Section 8 Enhanced Capture Timer ECT Block Description
Section 9 Analog to Digital Converter ATD Block Description
Section 13 J1850 BDLC Block Description
Description
Section 12 Serial Peripheral Interface SPI Block Description
Section 14 Byteflight BF Block Description
Section 20 Port Integration Module PIM Block Description
Section 18 RAM Block Description
Section 19 MSCAN Block Description
Section 21 Voltage Regulator VREG Block Description
Section 22 Printed Circuit Board Layout Proposal
Table 22-1 Suggested External Component Values
Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator
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Figure 22-2 Recommended PCB Layout for 80QFP Colpitts Oscillator
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Figure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator
C1 VSS1
MC9S12DT128B Device User Guide
Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator
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A.1 General
Appendix A Electrical Characteristics
A.1.2 Power Supply
A.1.1 Parameter Classification
A.1.3.1 5V I/O pins
A.1.3 Pins
A.1.4 Current Injection
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
A.1.6 ESD Protection and Latch-up Immunity
A.1.5 Absolute Maximum Ratings
Table A-1 Absolute Maximum Ratings1
Table A-3 ESD and Latch-Up Protection Characteristics
A.1.7 Operating Conditions
Table A-2 ESD and Latch-up Test Conditions
Table A-4 Operating Conditions
A.1.8 Power Dissipation and Thermal Characteristics
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The total power dissipation can be calculated from
Table A-5 Thermal Package Characteristics1
A.1.9 I/O Characteristics
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Table A-6 5V I/O Characteristics
2. Refer to Section A.1.4 Current Injection, for more details
A.1.10.1 Measurement Conditions
A.1.10 Supply Currents
A.1.10.2 Additional Remarks
Table A-7 Supply Current Characteristics
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A.2.2 Factors influencing accuracy
A.2 ATD Characteristics
A.2.1 ATD Operating Characteristics
Table A-8 ATD Operating Characteristics
A.2.2.3 Current injection
Table A-9 ATD Electrical Characteristics
A.2.2.2 Source capacitance
≥ 1024 * C
INLn = ∑ DNLi = Vn -V0 -n
A.2.3 ATD accuracy
1LSB
1LSB
Vi-1 LSB
Resolution
Figure A-1 ATD Accuracy Definitions
Vin mV
A.3.1.1 Single Word Programming
A.3 NVM, Flash and EEPROM
A.3.1 NVM timing
A.3.1.2 Burst Programming
Table A-11 NVM Timing Characteristics
t mass ≈
tcheck ≈ location ⋅ tcyc + 10 ⋅ tcyc
A.3.1.3 Sector Erase
A.3.2 NVM Reliability
Table A-12 NVM Reliability Characteristics
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Table A-13 Voltage Regulator Recommended Load Capacitances
A.4 Voltage Regulator
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Table A-14 Startup Characteristics
A.5 Reset, Oscillator and PLL
A.5.1 Startup
A.5.1.3 External Reset
A.5.1.5 Pseudo Stop and Wait Recovery
A.5.2 Oscillator
Table A-15 Oscillator Characteristics
K V = K 1 ⋅ e
A.5.3 Phase Locked Loop
XFC Pin
KΦ = -ich ⋅ KV
ζ =
2 ⋅ ζ ⋅ f ref
→ f C
ζ +
JN = j1 + j
J N = max ⎜
N ⋅ t nom
N ⋅ t nom
Δtrk
Table A-16 PLL Characteristics
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ΔLock
Table A-17 MSCAN Wake-up Pulse Characteristics
A.6 MSCAN
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Figure A-5 SPI Master Timing CPHA =
A.7.1 Master Mode
A.7 SPI
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Table A-18 SPI Master Mode Timing Characteristics1
Figure A-6 SPI Master Timing CPHA =1
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB
Figure A-8 SPI Slave Timing CPHA =1
A.7.2 Slave Mode
Figure A-7 SPI Slave Timing CPHA =
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MC9S12DT128B Device User Guide
Table A-19 SPI Slave Mode Timing Characteristics
Symbol
Rating
A.8 External Bus Timing
A.8.1 General Muxed Bus Timing
MC9S12DT128B Device User Guide
Figure A-9 General External Bus Timing
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Table A-20 Expanded Bus Timing Characteristics
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Table A-20 Expanded Bus Timing Characteristics
tNOH
B.1 General
Appendix B Package Information
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Figure 22-5 112-pin LQFP mechanical dimensions case no
B.2 112-pin LQFP package
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Figure 1 80-pin QFP Mechanical Dimensions case no. 841B
B.3 80-pin QFP package
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MC9S12DT128B Device User Guide
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MC9S12DT128B Device User Guide
User Guide End Sheet
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MC9S12DT128B Device User Guide
FINAL PAGE OF 124 PAGES
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