Motorola MC9S12DB128B manual A.5.3 Phase Locked Loop, XFC Pin, K V = K 1 ⋅ e, KΦ = -ich ⋅ KV

MC9S12DT128B Device User Guide — V01.07

A.5.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode.

A.5.3.1 XFC Component Selection

This section describes the selection of the XFC components to achieve a good filter characteristics.

			Cp
		VDDPLL
			Cs	R	XFC Pin
				Phase	VCO
fosc	1	fref	Δ	KΦ	fvco
	refdv+1				KV

fcmp

Detector

Loop Divider

11

synr+12

Figure A-2 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-16.

The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock.

The VCO Gain at the desired VCO frequency is approximated by:

(f1	–fvco )
-----------------------
K1 ⋅ 1V		⋅ e
KV = K1 ⋅ e	= –120

The phase detector relationship is given by:

KΦ = –ich⋅ KV

ich is the current in tracking mode.

(75 –50)

-----------------------

–120= -97.43MHz/V

=341.0Hz/Ω

105

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