dCS 974 User Manual

Manual for Software Version 1.0x

dCS Ltd

May 2001

dCS 974 TECHNICAL INFORMATION

Digital Data Formats Supported

dCS 974 provides nine digital data i/o formats:

AES/EBU

(often referred to as AES3) for PCM operation

Dual AES

(part of the AES3 spec) for PCM operation

Quad AES

(part of the AES3 spec) for PCM operation

SDIF-2

for PCM operation

SDIF-2

for DSD operation

SDIF-3

for DSD operation

DSD Quad

for DSD operation

SPDIF

(electrical) for PCM operation

SPDIF

(optical) for PCM operation

For all formats, the incoming Channel Status and User messages are discarded12. The unit allows the AES/EBU and SPDIF output Channel Status bits to be edited.

The enhanced AES/EBU interface is fully implemented. Each channel has its own parity and data validity bit, as well as User and Channel Status messages. Cyclic Redundancy Counts (CRC's) are generated from the Channel Status message.

The Dual AES interface allows an 88.2 or 96kS/s 24 bit signal to be coded as two standard 44.1 or 48kS/s 24 bit AES data streams, recorded as four tracks on a recorder with standard capacity, replayed and decoded back into a single data stream. Operation of the Dual AES interface at double speed allows the unit to input or output 2 wire 176.4 or 192 kS/s 24 bit data, and convert to and from this.

The Quad AES interface allows an 176.4 or 192kS/s 24 bit Dual AES data stream to be coded as four standard 44.1 or 48kS/s 24 bit AES data streams, recorded as eight tracks on a recorder with standard capacity. It may be replayed and converted into a Dual AES stream, a single wire format or DSD.

SDIF-2 PCM message bits are internally set to zero, with the exception of the block code, which is implemented.

The SPDIF interface has no CRC's - as per definition. Data formats for both SPDIF electrical and SPDIF optical are identical.

DSD has, at the time of writing, no messaging structure. Contact dCS for more details. Data formats use either the SDIF-2 system (two data channels and third clock channel), the SDIF-3 format (two data channels with embedded clock) or the DSD Quad format (four AES3 style data streams).

12At present we do this because there is no standard on what to do with the excess or shortage of bits that is created by a sample rate change. If this causes you a problem, call us – we can probably do something else, if we are clear what that ought to be.

Manual part no: DOC1241121A1

Page 70

Document No: OS-MA-A0124-112.1A1

Contact dCS on + 44 1799 531 999

email to: more@dcsltd.co.uk

(inside the UK replace + 44 with 0)

web site: www.dcsltd.co.uk